Method and system for accessing a flash memory device

• US 9,230,654 B2
• Filed: 03/08/2013
• Issued: 01/05/2016
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki, Pyeon, Hong Beom
• Primary Examiner(s): Nguyen, Tan
• Application Number:
  US13/790,361
• Publication Number:
  US 20130188422A1
• Time in Patent Office: 1,033 Days
• Field of Search: 365/221, 365/239, 365/185.11, 365/185.33, 365/189.05, 365/189.15, 365/230.03, 365/233.1
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Claims

1. A flash memory device comprising:

a flash memory array;

a page buffer to receive read data from the flash memory array;

a clock input pin to receive a clock signal; and

a data interface to provide the read data in the page buffer on a first number of first edges of the clock signal, and to receive command data at the data interface, the data interface including;

a common command and data input to receive input data and the command data at different times; and

a control input pin to receive a control signal set to a logic level for a same number of second edges of the clock signal as the first number of the first edges, and the control signal to enable the data interface to provide the read data.

2. The flash memory device of claim 1, wherein the first edges of the clock signal and the second edges of the clock signal are the same.

3. The flash memory device of claim 1, wherein the first number of clock edges is up to a maximum number of clock edges required for providing all data stored in the page buffer.

4. The flash memory device of claim 1, wherein the read data provided by the page buffer is between one byte and 2112 bytes in size.

5. The flash memory device of claim 1, wherein the read data is provided by the data interface within at least one clock cycle of the clock signal after the control signal has changed to the logic level.

6. The flash memory device of claim 1, wherein the read data includes read data provided by the flash memory array, or read data provided by another flash memory device as the input data.

7. The flash memory device of claim 1, wherein the data interface includes an output data pin to output the read data provided by the flash memory array, read data provided by another flash memory device, or the command data.

8. The flash memory device of claim 1, wherein the read data is provided by the data interface during each period of the clock signal.

9. The flash memory device of claim 1, wherein the clock signal is an input clock signal, and the flash memory device further includes a clock output pin to provide the input clock signal as an output clock signal.

10. The flash memory device of claim 1, wherein the read data is provided serially as a single-bit-wide data stream.

11. The flash memory device of claim 1, wherein the input data includes write data provided to the flash memory array.

12. The flash memory device of claim 1, wherein the control signal has one logic level for enabling outputting of the read data from the data interface, and

outputting of the read data by the data interface is disabled when the control signal has another logic level.

13. The flash memory device of claim 1, wherein the data interface outputs the read data serially while the control signal is at the one logic level.

14. The flash memory device of claim 1, wherein the data interface receives as input data, a read address.

15. The flash memory device of claim 14, wherein the read address is received by the common command and data input during each period of the clock signal.

16. The flash memory device of claim 1, wherein the clock signal is a free-running clock signal.

17. A method of operating a flash memory device, comprising:

receiving a control signal at a data interface in communication with a flash memory bank, the control signal being set to a logic level for a first number of first edges of a clock signal for enabling read data loaded into a page buffer to be output by the data interface;

outputting the read data from the data interface in synchronization with the clock signal for the same number of second edges of the clock signal as the first number of the first edges; and

receiving command data at a common command and data input of the data interface in synchronization with the clock signal, the common command and data input being configured to receive input data and the command data at different times.