Finding read disturbs on non-volatile memories

• US 9,230,689 B2
• Filed: 03/17/2014
• Issued: 01/05/2016
• Est. Priority Date: 03/17/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Tuers, Daniel, Ataklti, Yosief, Manohar, Abhijeet
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US14/215,924
• Publication Number:
  US 20150262714A1
• Time in Patent Office: 659 Days
• Field of Search: 365/230.01, 365/185.11, 365/185.12, 365/185.13, 365/189.011, 365/189.15, 365/230.03, 365/239
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

In non-volatile memory devices, the accessing of data on word line can degrade the data quality on a neighboring word line, in what is called a read disturb. Techniques are presented for determining word lines likely to suffer read disturbs by use of a hash tree for tracking the number of reads. Read counters are maintained for memory units at a relatively coarse granularity, such as a die or block. When the counter for one of these units reaches a certain level, it is subdivided into sub-units, each with their own read counter, in a process that be repeated to determine frequently read word lines with a fine level of granularity while only using a relatively modest amount of RAM on the controller to store the counters.

Claims

1. A method of operating a non-volatile memory system having one or more memory circuits and a controller circuit, the memory circuits each including one or more arrays of non-volatile memory cells formed along word lines and the controller circuit managing the storage of data on the memory circuit, the method comprising:

for each of a first plurality of distinct divisions of the one or more memory arrays maintaining by the controller circuit a count of the number of times word lines of the corresponding division are accessed for a read operation;

in response to one of the counts for a corresponding division reaching a first threshold value, subdividing the corresponding division into a second plurality of distinct first subdivisions; and

subsequently maintaining by the controller circuit for each of the first subdivisions a count of the number of times word lines of the subdivision are accessed for read operations.

2. The method of claim 1, further comprising:

in response to one of the counts for a corresponding subdivision reaching a second threshold value, further subdividing the corresponding subdivision into a third plurality of distinct first sub-subdivisions; and

subsequently maintaining by the controller circuit for each of the first sub-subdivisions a count of the number of times word lines of the sub-subdivision are accessed for read operations.

3. The method of claim 1, wherein the first plurality of distinct divisions were previously formed by subdividing one of a plurality of structures formed of such divisions in response to a number of accesses for read operations.

4. The method of claim 1, further comprising:

in response to one of the counts for a corresponding subdivision reaching a second threshold value, placing the corresponding one of the subdivisions a list of subdivisions on which to perform a data scrub operation.

5. The method of claim 1, further comprising:

in response to one of the counts for a corresponding subdivision reaching a second threshold value, performing a scrub operation on the corresponding one of the subdivisions.

6. The method of claim 1, further comprising:

in response to one of the counts for a corresponding subdivision reaching a second threshold value, relocating the data from the corresponding one of the subdivisions to a different location on the memory circuits.

7. The method of claim 6, wherein the different location on the memory circuits is reserved by the controller circuit for frequently accessed data.

8. The method of claim 7, wherein the location reserved by the controller circuit for frequently accessed data is managed differently by the controller circuit than other portions of the memory circuits.

9. The method of claim 8, wherein data is stored in a binary format in the location reserved for frequently accessed data.

10. The method of claim 8, wherein data is stored on non-adjacent word lines in the location reserved for frequently accessed data.

11. The method of claim 7, wherein the relocated data is subsequently evicted from the location reserved for frequently accessed data in response to determining that the frequency of being accessed for the relocated data is decreased.

12. The method of claim 6, wherein the data relocated includes one or more frequently accessed word lines and one or more word lines adjacent the frequently accessed word lines.

13. The method of claim 6, wherein the relocating the data from the corresponding one of the subdivisions includes the relocation of an entire erase block.

14. The method of claim 1, wherein the controller circuit includes a volatile memory in which are maintained the values of the counts.

15. The method of claim 14, wherein the controller circuit periodically saves the count values to non-volatile memory on the memory circuits.

16. The method of claim 15, wherein on power up, the controller circuit loads the count values saved in non-volatile memory into the volatile memory on the controller circuit.

17. The method of claim 1, wherein the memory circuits are flash memory circuit and the divisions correspond to a plurality of erase blocks.

18. The method of claim 1, wherein the memory circuits are flash memory circuit and the subdivisions correspond to a plurality of erase blocks.

19. The method of claim 1, wherein the memory circuits are flash memory circuit and the divisions correspond to an erase blocks.

20. The method of claim 1, further comprising:

subsequently discontinuing of the maintaining by the controller circuit for one or more of the first subdivisions the count of the number of times word lines of the subdivision are accessed for read operations.

21. The method of claim 20, wherein the discontinuing is in response to the value of the counts being discontinued relative to others of the counts of the first subdivision.

22. The method of claim 20, wherein the discontinuing is in response to the corresponding division being erased.

23. The method of claim 20, wherein the discontinuing is in response to the number of counts being maintained.

24. The method of claim 1, wherein the memory circuits are flash memory circuit and the subdivisions correspond to an erase blocks.

25. The method of claim 1, wherein the divisions correspond to a set of word lines.

26. The method of claim 1, wherein the subdivisions correspond to a set of word lines.

27. The method of claim 1, wherein the memory circuits include a plurality of dies and the divisions correspond to a die.

28. The method of claim 1, wherein the arrays are of a NAND-type of architecture.

29. The memory of claim 1, wherein the arrays are of an architecture having a three dimensional memory array that is monolithically formed as a plurality of physical levels of memory cells, a physical level having an active layer disposed above a silicon substrate, the memory cells in communication with operating circuitry.