One-time programmable memory and method for making the same

• US 9,230,813 B2
• Filed: 04/10/2014
• Issued: 01/05/2016
• Est. Priority Date: 06/21/2010
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Kilopass Technology Incorporated (Synopsys Incorporated)
• Inventors: Luan, Harry Shengwen
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US14/250,267
• Publication Number:
  US 20140217484A1
• Time in Patent Office: 635 Days
• Field of Search: 257/209
• US Class Current: 1/1
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.

Claims

1. A one-time programmable non-volatile memory cell formed by a semiconductor process having a minimum feature size of F, comprising:

a buried bitline formed in a substrate, the buried bitline of a first conductivity type and defined by a width no more than F;

a dielectric layer formed over at least a portion of the buried bitline; and

a conductive gate formed over the dielectric layer, the conductive gate formed over a channel region under the conductive gate and dielectric layer;

wherein the channel region does not have electrical interaction other than to said buried bitline or conductive gate.

2. The memory cell of claim 1 wherein formed on the sidewalls of the conductive gate are sidewall spacers.

3. The memory cell of claim 1 wherein the conductive gate has a second conductivity type different from the first conductivity type.

4. The memory cell of claim 3 wherein between the conductive gate of the memory cell and the conductive gate of an adjacent memory cell there are no floating regions of second conductivity type.

5. The memory cell of claim 1 wherein the buried bitline has a graded dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

6. The memory cell of claim 1 wherein said dielectric layer is thicker proximal to at least a portion of the edge of the channel region than to the center of the channel region.

7. A one-time programmable non-volatile memory cell formed by a semiconductor process having a minimum feature size of F, comprising:

a buried bitline formed in a substrate, the buried bitline of a first conductivity type and defined by a width no more than F;

a dielectric layer formed over at least a portion of the buried bitline; and

a conductive metal gate formed over the dielectric layer, the conductive metal gate formed over a channel region under the conductive metal gate and dielectric layer;

wherein the channel region does not have electrical interaction other than to said buried bitline or conductive metal gate.

8. The memory cell of claim 7 wherein formed on the sidewalls of the conductive metal gate are sidewall spacers.

9. The memory cell of claim 7 wherein the buried bitline has a graded dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

10. The memory cell of claim 9 wherein between the conductive metal gate of the memory cell and the conductive metal gate of an adjacent memory cell there are doped regions of the first conductivity type having a dopant concentration higher than said lower dopant concentration.

11. The memory cell of claim 10 further including a shallow doped layer of a second conductivity type between said dielectric layer and said buried bitline.

12. The memory cell of claim 7 wherein said dielectric layer is thicker proximal to at least a portion of the edge of the channel region than to the center of the channel region.

13. The memory cell of claim 7 wherein between the conductive metal gate of the memory cell and the conductive metal gate of an adjacent memory cell there are no floating regions of a second conductivity type.

14. The memory cell of claim 7 further including a shallow doped layer of a second conductivity type between said dielectric layer and said buried bitline.

15. A one-time programmable non-volatile memory cell formed by a semiconductor process having a minimum feature size of F, comprising:

a buried bitline formed in a substrate, the buried bitline of a first conductivity type;

a dielectric layer formed over at least a portion of the buried bitline; and

a conductive gate formed over the dielectric layer, the conductive gate formed over a channel region under the conductive gate and dielectric layer and defined by a width no more than F;

wherein the channel region does not have electrical interaction other than to said buried bitline or conductive gate.

16. The memory cell of claim 15 wherein formed on the sidewalls of the conductive gate are sidewall spacers.

17. The memory cell of claim 15 wherein the conductive gate has a second conductivity type different from the first conductivity type.

18. The memory cell of claim 17 wherein between the conductive gate of the memory cell and the conductive gate of an adjacent memory cell there are no floating regions of second conductivity type.

19. The memory cell of claim 15 wherein the buried bitline has a graded dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

20. The memory cell of claim 15 wherein said dielectric layer is thicker proximal to at least a portion of the edge of the channel region than to the center of the channel region.

21. The memory cell of claim 15 wherein the buried bitline has a width no more than F.

30. The memory cell of claim 18 wherein the buried bitline has a width no more than F.

22. A one-time programmable non-volatile memory cell formed by a semiconductor process having a minimum feature size of F, comprising:

a buried bitline formed in a substrate, the buried bitline of a first conductivity type;

a dielectric layer formed over at least a portion of the buried bitline; and

a conductive metal gate formed over the dielectric layer, the conductive metal gate formed over a channel region under the conductive metal gate and dielectric layer and defined by a width no more than F;

wherein the channel region does not have electrical interaction other than to said buried bitline or conductive metal gate.

23. The memory cell of claim 22 wherein formed on the sidewalls of the conductive metal gate are sidewall spacers.

24. The memory cell of claim 22 wherein the buried bitline has a graded dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

25. The memory cell of claim 24 wherein between the conductive metal gate of the memory cell and the conductive metal gate of an adjacent memory cell there are doped regions of the first conductivity type and having a dopant concentration higher than said lower dopant concentration.

26. The memory cell of claim 25 further including a shallow doped layer of a second conductivity type between said dielectric layer and said buried bitline.

27. The memory cell of claim 22 wherein said dielectric layer is thicker proximal to at least a portion of the edge of the channel region than to the center of the channel region.

28. The memory cell of claim 22 wherein between the conductive metal gate of the memory cell and the conductive metal gate of an adjacent memory cell there are no floating regions of a second conductivity type.

29. The memory cell of claim 22 further including a shallow doped layer of a second conductivity type between said dielectric layer and said buried bitline.

31. A one-time programmable non-volatile memory cell comprising:

a buried bitline formed in a substrate, the buried bitline of a first conductivity type;

a dielectric layer formed over at least a portion of the buried bitline; and

a conductive gate formed over the dielectric layer and having a second conductivity type different from the first conductivity type, the conductive gate formed over a channel region under the conductive gate and dielectric layer;

wherein the channel region does not have electrical interaction other than to said buried bitline or conductive gate.

32. The memory cell of claim 31 wherein between the conductive gate of the memory cell and the conductive gate of an adjacent memory cell there are no floating regions of second conductivity type.