Reduction of polysilicon residue in a trench for polysilicon trench filling processes

• US 9,230,851 B2
• Filed: 02/07/2014
• Issued: 01/05/2016
• Est. Priority Date: 02/07/2013
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Molloy, Simon John, Kocon, Christopher Boguslaw, Neilson, John Manning Savidge, Yang, Hong, Sridhar, Seetharaman, Kawahara, Hideaki
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): ASSOUMAN, HERVE-LOUIS Y
• Application Number:
  US14/175,488
• Publication Number:
  US 20140220761A1
• Time in Patent Office: 697 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A method of fabricating a semiconductor device includes forming at least one trench from a top side of a semiconductor layer, wherein the trench is lined with a trench dielectric liner and filled by a first polysilicon layer. The surface of the trench dielectric liner is etched, wherein dips in the trench dielectric liner are formed relative to a top surface of the first polysilicon layer which results in forming a protrusion including the first polysilicon layer. The first polysilicon layer is etched to remove at least a portion of the protrusion. A second dielectric layer is formed over at least the trench after etching the first polysilicon layer. A second polysilicon layer is deposited. The second polysilicon layer is etched to remove it over the trench and provide a patterned second polysilicon layer on the top side of the semiconductor layer.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming at least one trench from a top side of a semiconductor surface, wherein said trench is lined with a trench dielectric liner and filled by a first polysilicon layer;

etching a surface of said trench dielectric liner, wherein dips are formed relative to a top surface of said first polysilicon layer which form a polysilicon protrusion comprising said first polysilicon layer;

etching said first polysilicon layer to remove at least a portion of said polysilicon protrusion;

forming a second dielectric layer over at least said trench after etching said first polysilicon layer;

depositing a second polysilicon layer, and

etching said second polysilicon layer to remove said second polysilicon layer over said trench and provide a patterned second polysilicon layer without substantially recessing from said top side of said semiconductor surface.

2. The method of claim 1, wherein said etching said first polysilicon layer comprises reactive ion etching (RIE), plasma etching, or a wet chemical etching.

3. The method of claim 1, wherein said trench dielectric liner comprises silicon oxide.

4. The method of claim 2, wherein said wet chemical etching said surface of said trench dielectric liner comprises a hydrofluoric acid (HF) solution etch.

5. The method of claim 3, wherein said second dielectric layer comprises a tetraethyl orthosilicate (TEOS) derived layer of silicon oxide.

6. The method of claim 1, wherein said forming at least one trench comprises forming a termination trench and forming a plurality of active area trenches surrounded by said termination trench, and wherein said etching said second polysilicon layer removes said second polysilicon layer from said termination trench but not from said plurality of active area trenches.

7. The method of claim 6, wherein a depth of said plurality of active area trenches and said termination trench are all between 2 μ

m and 20 μ

m.

8. The method of claim 6, wherein said plurality of active area trenches are adjacent to gate electrodes comprising a third polysilicon layer on a gate dielectric.

9. The method of claim 1, wherein said forming said second dielectric layer comprises depositing.

10. The method of claim 1, wherein said semiconductor surface comprises silicon.

11. The method of claim 1, wherein said semiconductor device comprises a discrete n-channel MOSFET.

12. A method of fabricating a semiconductor device, comprising:

forming a termination trench and forming a plurality of active area trenches surrounded by said termination trench from a top side of a silicon surface,

lining said termination trench and said plurality of active area trenches with a trench dielectric liner;

filling said termination trench and said plurality of active area trenches with a first polysilicon layer,

etching a surface of said trench dielectric liner, wherein dips in said trench dielectric liner are formed relative to a top surface of said first polysilicon layer which form a protrusion comprising said first polysilicon layer in said termination trench;

etching said first polysilicon layer to remove at least a portion of said protrusion;

forming a second dielectric layer over at least said termination trench after etching said first polysilicon layer;

depositing a second polysilicon layer, and

etching said second polysilicon layer to remove said second polysilicon layer over said termination trench and provide a patterned second polysilicon layer without substantially recessing from said top side of said silicon surface.