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Method of forming 3D integrated microelectronic assembly with stress reducing interconnects

  • US 9,230,947 B2
  • Filed: 08/29/2013
  • Issued: 01/05/2016
  • Est. Priority Date: 06/09/2011
  • Status: Active Grant
First Claim
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1. A method of forming a microelectronic assembly, comprising:

  • providing a first microelectronic element that comprises;

    a substrate with first and second opposing surfaces,a semiconductor device integrally formed on or in the first surface of the substrate, andconductive pads at the first surface which are electrically coupled to the semiconductor device;

    providing a second microelectronic element comprising;

    a handler with first and second opposing surfaces, and a cavity formed into the first surface that extends toward but does not reach the second surface,an IC chip disposed in the cavity and having a bottom surface with conductive pads facing away from the second surface;

    forming conductive elements each extending from one of the conductive pads and through the substrate to the second surface, of the first microelectronic element;

    forming conductive elements each extending between the first and second surfaces of the handler;

    integrating the first and second microelectronic elements to each other such that the second surfaces face each other and such that each of the conductive elements of the first microelectronics element is electrically coupled to at least one of the conductive elements of the second microelectronics element;

    forming electrical interconnects over the first surface of the handler with each electrically coupled to at least one of the conductive elements of the second microelectronics element; and

    forming electrical interconnects over the bottom surface of the IC chip with each electrically coupled to at least one of the conductive pads of the IC chip.

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