Method of forming 3D integrated microelectronic assembly with stress reducing interconnects

• US 9,230,947 B2
• Filed: 08/29/2013
• Issued: 01/05/2016
• Est. Priority Date: 06/09/2011
• Status: Active Grant

• Current Assignee: Optiz, Inc.
• Original Assignee: Optiz, Inc.
• Inventors: Oganesian, Vage
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US14/013,317
• Publication Number:
  US 20140004647A1
• Time in Patent Office: 859 Days
• Field of Search: 438/67, 257/443, 257/E31.124, 257/686
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device

Abstract

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

Claims

1. A method of forming a microelectronic assembly, comprising:

providing a first microelectronic element that comprises;

a substrate with first and second opposing surfaces,

a semiconductor device integrally formed on or in the first surface of the substrate, and

conductive pads at the first surface which are electrically coupled to the semiconductor device;

providing a second microelectronic element comprising;

a handler with first and second opposing surfaces, and a cavity formed into the first surface that extends toward but does not reach the second surface,

an IC chip disposed in the cavity and having a bottom surface with conductive pads facing away from the second surface;

forming conductive elements each extending from one of the conductive pads and through the substrate to the second surface, of the first microelectronic element;

forming conductive elements each extending between the first and second surfaces of the handler;

integrating the first and second microelectronic elements to each other such that the second surfaces face each other and such that each of the conductive elements of the first microelectronics element is electrically coupled to at least one of the conductive elements of the second microelectronics element;

forming electrical interconnects over the first surface of the handler with each electrically coupled to at least one of the conductive elements of the second microelectronics element; and

forming electrical interconnects over the bottom surface of the IC chip with each electrically coupled to at least one of the conductive pads of the IC chip.

2. The method of claim 1, the forming of each of the conductive elements of the first microelectronic element comprises:

forming a hole in the substrate with a sidewall extending from the second surface of the substrate to one of the conductive pads of the first microelectronic element;

forming a compliant dielectric material disposed along the sidewall; and

forming a conductive material disposed along the compliant dielectric material and extending between the second surface of the substrate and the one conductive pad of the first microelectronic element.

3. The method of claim 2, wherein the compliant dielectric material includes a polymer.

4. The method of claim 2, wherein for each of the conductive elements of the first microelectronic element, the hole is tapered such that the hole has a smaller cross-sectional dimension at the one conductive pad than at the second surface of the substrate.

5. The method of claim 2, wherein for each of the conductive elements of the first microelectronic element, the sidewall extends in a direction between 5°

and 35°

relative to a direction that is perpendicular to the first and second surfaces of the substrate.

6. The method of claim 1, wherein the forming of each of the conductive elements of the second microelectronic element comprises:

forming a hole in the handler with a sidewall extending between the first and second surfaces of the handler;

forming a compliant dielectric material disposed along the sidewall; and

forming a conductive material disposed along the compliant dielectric material and extending between the first and second surfaces of the handler.

7. The method of claim 6, wherein the compliant dielectric material includes a polymer.

8. The method of claim 6, wherein for each of the conductive elements of the second microelectronic element, the hole is tapered such that the hole has a smaller cross-sectional dimension at the second surface than at the first surface of the handler.

9. The method of claim 6, wherein for each of the conductive elements of the second microelectronic element, the sidewall extends in a direction between 5°

and 35°

relative to a direction that is perpendicular to the first and second surfaces of the handler.

10. The method of claim 1, wherein the semiconductor device of the first microelectronic assembly is an image sensor and the IC chip of the second microelectronic assembly is a processor for processing signals from the image sensor.

11. The method of claim 10, wherein the image sensor comprises an array of pixel sensors each including a photodetector for converting light energy to a voltage signal, and wherein the processor is configured to receive the voltage signals and to compute or interpolate color and brightness values for each of the voltage signals from the pixel sensors.

12. The method of claim 1, wherein the integration comprises:

forming a plurality of BGA interconnects each electrically coupled between one of the conductive pads of the first microelectronic elements and one of the conductive pads of the second microelectronic elements.