High dielectric constant etch stop layer for a memory structure

• US 9,230,979 B1
• Filed: 10/31/2014
• Issued: 01/05/2016
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Pachamuthu, Jayavel, Alsmeier, Johann
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US14/530,220
• Time in Patent Office: 431 Days
• Field of Search: 438257-267, 438/396, 257314-321
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A high dielectric constant (high-k) dielectric material layer having a dielectric constant greater than 7.9 is formed a substrate. A stack of alternating layers comprising first material layers and second material layers is formed over the high-k dielectric material layer. A memory opening is formed through the stack employing a top surface of the high-k dielectric material layer as an etchstop layer, thereby minimizing an overetch. A memory film and a semiconductor channel are subsequently formed. During formation of a backside contact trench, the high-k dielectric material layer can be employed as an etch stop layer. Thus, the high-k dielectric material layer can be employed as a common etch stop layer for formation of the memory opening and the backside contact trench.

Claims

1. A monolithic three-dimensional memory device, comprising:

a high dielectric constant (high-k) dielectric material layer having a dielectric constant greater than 7.9 and located over a substrate;

a stack of alternating layers comprising insulator layers and electrically conductive layers and located over the high-k dielectric material layer;

a memory opening extending through the stack; and

a memory film and a semiconductor channel located within the memory opening, wherein;

the memory film is in contact with a top surface of the high-k dielectric material layer; and

a portion of the semiconductor channel extends through an opening in the high-k dielectric material layer and contacts a semiconductor material within the substrate.

2. The monolithic three-dimensional memory device of claim 1, wherein the high-k dielectric material layer comprises a dielectric metal oxide.

3. The monolithic three-dimensional memory device of claim 1, wherein the high-k dielectric material layer comprises an aluminum oxide layer.

4. The monolithic three-dimensional memory device of claim 1, wherein the high-k dielectric material layer is a horizontal layer having a topmost surface located below a horizontal plane including a top surface of a bottommost electrically conductive layer within the stack.

5. The monolithic three-dimensional memory device of claim 1, wherein the memory film comprises a blocking dielectric layer extending through the stack and including a horizontal portion having a bottom surface that contacts a top surface of the high-k dielectric material layer.

6. The monolithic three-dimensional memory device of claim 5, wherein a sidewall of the high-k dielectric material layer at the opening is vertically coincident with a sidewall of the blocking dielectric layer.

7. The monolithic three-dimensional memory device of claim 5, wherein the memory film further comprises a plurality of blocking dielectric portions having an annular shape, contacting the blocking dielectric layer, and surrounding the blocking dielectric layer.

8. The monolithic three-dimensional memory device of claim 7, wherein a periphery of the high-k dielectric material layer is laterally recessed inward from an outer sidewall of a bottommost blocking dielectric portion among the plurality of blocking dielectric portions.

9. The monolithic three-dimensional memory device of claim 5, wherein the memory film further comprises:

at least one charge storage element located on an inner sidewall of the blocking dielectric layer; and

a tunneling dielectric contacting the at least one charge storage element and the semiconductor channel.

10. The monolithic three-dimensional memory device of claim 1, wherein a sidewall of the semiconductor channel is in contact with a sidewall of the high-k dielectric material layer at the opening.

11. The monolithic three-dimensional memory device of claim 1, further comprising:

a source region located within the substrate; and

a source contact via structure extending through the stack and contacting the source region.

12. The monolithic three-dimensional memory device of claim 11, further comprising an insulating spacer extending through the stack and laterally surrounding the source contact via structure.

13. The monolithic three-dimensional memory device of claim 12, further comprising at least one backside blocking dielectric layer contacting each of the electrically conductive layers and the insulating spacer.

14. The monolithic three-dimensional memory device of claim 13, wherein the backside blocking dielectric layer comprises a silicon oxide layer.

15. The monolithic three-dimensional memory device of claim 13, wherein the backside blocking dielectric layer comprises an additional high-k dielectric material layer.

16. The monolithic three-dimensional memory device of claim 12, further comprising a dielectric pad layer located over the substrate and including an opening therein, wherein the insulating spacer contacts a sidewall of the opening of the dielectric pad layer.

17. The monolithic three-dimensional memory device of claim 16, wherein the sidewall of the opening of the dielectric pad layer is vertically coincident with an inner sidewall of the insulating spacer.

18. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a vertical NAND device located in a device region; and

the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device.

19. The three-dimensional memory device of claim 18, wherein:

the device region comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;

the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

20. A method of manufacturing a three-dimensional memory structure, comprising:

forming a high dielectric constant (high-k) dielectric material layer having a dielectric constant greater than 7.9 over a substrate;

forming a stack of alternating layers comprising first material layers and second material layers over the high-k dielectric material layer;

forming a memory opening through the stack employing the high-k dielectric material layer as an etchstop layer;

forming a memory film in the memory opening;

forming an extension of the memory opening by an anisotropic etch of the high-k dielectric material layer employing at least the memory film as an etch mask, wherein the extension of the memory opening extends to the substrate; and

forming a semiconductor channel on the memory film, wherein the semiconductor channel extends through the extension opening in the high-k dielectric material layer and contacts the substrate.

21. The method of claim 20, further comprising forming a backside opening through the stack employing the high-k dielectric material layer as an etchstop layer.

22. The method of claim 20, wherein the memory film is formed directly on a top surface of the high-k dielectric material layer.

23. The method of claim 20, wherein forming the high-k dielectric material layer comprises depositing a dielectric metal oxide layer.

24. The method of claim 20, wherein forming the high-k dielectric material layer comprises depositing an aluminum oxide layer.

25. The method of claim 20, wherein a bottommost surface of the stack is formed on a topmost surface of the high-k dielectric material layer.

26. The method of claim 20, wherein forming the memory film comprises forming a blocking dielectric layer directly on a top surface of the high-k dielectric material layer employing a conformal deposition method.

27. The method of claim 26, wherein the second material layers comprise silicon nitride, and the method further comprises forming a plurality of blocking dielectric portions comprising a silicon oxynitride or silicon oxide and having an annular shape around the memory opening prior to formation of the blocking dielectric layer.

28. The method of claim 26, wherein forming the memory film further comprises:

forming at least one charge storage element on an inner sidewall of the blocking dielectric layer; and

forming a tunneling dielectric directly on the at least one charge storage element.

29. The method of claim 20, further comprising:

forming a backside contact trench through the stack employing the high-k dielectric material layer as an etchstop layer; and

removing the second material layers by introducing an etchant that etches the second material layers through the backside contact trench, wherein backside recesses are formed in volumes previously occupied by the second material layers.

30. The method of claim 29, further comprising removing a portion of the high-k dielectric material layer that underlies a bottommost backside recess among the backside recesses.

31. The method of claim 30, wherein a peripheral sub-portion of a horizontal portion of the high-k dielectric material layer underlying the memory film is undercut during the removal of the portion of the high-k dielectric material layer that underlies the bottommost backside recess.

32. The method of claim 30, further comprising:

depositing at least one conductive material in the backside recesses and at a periphery of the backside contact trench; and

removing a portion of the deposited at least one conductive material from the periphery of the backside contact trench, wherein remaining portions of the at least one conductive material in the backside recesses constitute electrically conductive layers.

33. The method of claim 32, further comprising:

forming an insulating spacer at the periphery of the backside contact trench after formation of the electrically conductive layers;

extending a cavity within the insulating spacer vertically to a top surface of the substrate by an anisotropic etch;

forming a source region in the substrate underneath the vertically extended cavity; and

forming a source contact via structure in the vertically extended trench.

34. The method of claim 32, further comprising forming at least one backside blocking dielectric layer within the backside recesses prior to depositing the at least one conductive material, wherein the at least one backside blocking dielectric layer comprises at least one of a silicon oxide layer and an additional high-k dielectric material layer.

35. The method of claim 32, further comprising forming a stack of a silicon oxide layer and an additional high-k dielectric material layer within the backside recesses prior to depositing the at least one conductive material.

36. The method of claim 20, further comprising forming a device on the substrate by replacing the second material layers with electrically conductive portions, wherein:

the device comprises a vertical NAND device; and

at least one of the electrically conductive portions in the stack comprises, or is electrically connected to, a word line of the vertical NAND device.

37. The method of claim 36, wherein:

the NAND device comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;

the electrically conductive portions in the stack comprise, or are in electrical contact with, the plurality of control gate electrodes and extend from the device region to a contact region containing the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.