Hybrid CMOS nanowire mesh device and FINFET device

• US 9,230,989 B2
• Filed: 03/02/2014
• Issued: 01/05/2016
• Est. Priority Date: 12/16/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Chang, Josephine B., Chang, Leland, Lin, Chung-Hsun, Sleight, Jeffrey W.
• Primary Examiner(s): Patel, Reema
• Application Number:
  US14/194,762
• Publication Number:
  US 20140175374A1
• Time in Patent Office: 674 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.

Claims

1. A semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate comprising:

a first portion of the SOI substrate containing at least one nanowire mesh device and a second portion of the SOI substrate containing at least one FINFET device;

the at least one nanowire mesh device comprising;

a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;

a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region and a trench isolation region;

the at least one FINFET device comprising;

a plurality of spaced apart fins on a top semiconductor layer on the second portion of the substrate;

a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of fins and a trench isolation region;

wherein the SOI substrate comprises a semiconductor base, a buried insulating layer and a top semiconductor layer such that a thickness of the top semiconductor layer in the second portion is greater than the top semiconductor layer in the first portion and the top semiconductor layer in the first portion and the second portion makes direct contact with the trench isolation region in the nanowire mesh device and the at least one FINFET device respectively.

2. The semiconductor hybrid structure of claim 1 wherein the first portion of the SOI substrate containing a plurality of nanowire mesh devices and the second portion of the SOI substrate containing a plurality of FINFET devices.

3. The semiconductor hybrid structure of claim 1 wherein the thickness of the top semiconductor layer in the second portion is 60 to 90 nanometers and the thickness of the top semiconductor layer in the first portion is 30 to 90 nanometers.

4. The semiconductor hybrid structure of claim 1 wherein each of said semiconductor nanowires has a pitch of less than 200 nm and a width of less than 40 nm.

5. The semiconductor hybrid structure of claim 1 wherein each of said semiconductor nanowires comprises a Si-containing semiconductor material.

6. The semiconductor hybrid structure of claim 1 further comprising a spacer located adjacent to the gate region in the first and second portions of the SOI substrate.

7. The semiconductor hybrid structure of claim 6 wherein each spacer comprises a material selected from the group consisting of a nitride, an oxynitride and an oxide.

8. The semiconductor hybrid structure of claim 1 wherein the SOI substrate comprises a plurality of SOI chips and wherein the at least one nanowire mesh device and the at least one FINFET device are on the same chip.

9. The semiconductor hybrid structure of claim 8 wherein the at least one nanowire mesh device is adjacent to the at least one FINFET device.

10. A semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate comprising:

the SOI substrate comprising a bottom semiconductor layer, a buried insulating layer and a top semiconductor layer;

a first portion of the SOI substrate containing at least one nanowire mesh device and a second portion of the SOI substrate containing at least one FINFET device;

the at least one nanowire mesh device comprising;

a plurality of stacked and spaced apart semiconductor nanowires located on the substrate such that a plurality of the semiconductor nanowires are in direct contact with the buried insulating layer, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;

a gate region over at least a portion of the plurality of stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region and a trench isolation region;

the at least one FINFET device comprising;

a plurality of spaced apart fins formed from the top semiconductor layer on the second portion of the substrate;

a gate region over at least a portion of the plurality of fins and a trench isolation region extending upward from the buried insulating layer to isolate the FINFET device from another FINFET device and from the at least one nanowire mesh device;

wherein a thickness of the top semiconductor layer in the second portion is greater than the top semiconductor layer in the first portion and the top semiconductor layer in the first portion and the second portion makes direct contact with the trench isolation region in the nanowire mesh device and the at least one FINFET device respectively.

11. An integrated circuit comprising:

a semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate, the semiconductor hybrid structure comprising;

first portions of the SOI substrate containing a plurality of nanowire mesh devices and second portions of the SOI substrate containing a plurality of FINFET devices;

each of the plurality of nanowire mesh devices comprising;

a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;

a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region; and

a trench isolation region;

each of the plurality of FINFET devices comprising;

a plurality of spaced apart fins on a top semiconductor layer on the second portion of the substrate;

a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of fins; and

a trench isolation region;

wherein the SOI substrate comprises a semiconductor base, a buried insulating layer and a top semiconductor layer such that a thickness of the top semiconductor layer in the second portion is greater than the top semiconductor layer in the first portion and the top semiconductor layer in the first portion and the second portion makes direct contact with the trench isolation region in the nanowire mesh device and the at least one FINFET device respectively.

12. The integrated circuit of claim 11 wherein the thickness of the top semiconductor layer in the second portion is 60 to 90 nanometers and the thickness of the top semiconductor layer in the first portion is 30 to 90 nanometers.

13. The integrated circuit of claim 11 wherein each of said semiconductor nanowires has a pitch of less than 200 nm and a width of less than 40 nm.

14. The integrated circuit of claim 11 wherein each of said semiconductor nanowires comprises a Si-containing semiconductor material.

15. The integrated circuit of claim 11 further comprising a spacer located adjacent to the gate region in the first portions and the second portions of the SOI substrate.

16. The integrated circuit of claim 15 wherein each spacer comprises a material selected from the group consisting of a nitride, an oxynitride and an oxide.

17. The integrated circuit of claim 11 wherein the SOI substrate comprises a plurality of SOI chips and wherein there is at least one nanowire mesh device and at least one FINFET device on the same SOI chip.

18. The integrated circuit of claim 17 wherein the at least one nanowire mesh device is adjacent to the at least one FINFET device.