Semiconductor switching device with different local cell geometry

• US 9,231,049 B1
• Filed: 06/20/2014
• Issued: 01/05/2016
• Est. Priority Date: 06/20/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Fachmann, Christian, Vecino Vazquez, Enrique
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US14/309,977
• Publication Number:
  US 20150372076A1
• Time in Patent Office: 564 Days
• Field of Search: 257/132, 257/618, 257/263, 257139-140, 257/330, 257295-296, 257/340, 257/77, 257/691, 326/63, 345/89, 345/690
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. A source metallization is in ohmic contact with the source regions of the switchable cells. A gate metallization is in ohmic contact with the gate electrode structures of the switchable cells. The active area defined by the switchable cells includes at least a first switchable region having a specific gate-drain capacitance which is different to a specific gate-drain capacitance of a second switchable region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim, wherein each of the switchable cells comprises a body region, a gate electrode structure and a source region;

a source metallization in ohmic contact with the source regions of the switchable cells; and

a gate metallization in ohmic contact with the gate electrode structures of the switchable cells;

wherein the active area defined by the switchable cells comprises at least a first switchable region having a specific gate-drain capacitance which is different to a specific gate-drain capacitance of a second switchable region.

2. The semiconductor device of claim 1, wherein the second switchable region is arranged between the gate metallization and the first switchable region, wherein the second switchable region has a higher specific gate-drain capacitance than the first switchable region.

3. The semiconductor device of claim 1, wherein the gate-drain capacitance of switchable cells in the first and second switchable region decreases step-wise from the second switchable region arranged next to the gate metallization to the first switchable region arranged in a central region of the active area further away from the gate metallization.

4. The semiconductor device of claim 1, wherein the gate metallization comprises an electrically conductive structure selected from the group consisting of a gate runner structure, a gate pad, a gate ring, a gate finger, and any combination thereof.

5. The semiconductor device of claim 1, wherein the plurality of switchable cells comprises at least one transistor selected from the group consisting of a MOSFET, a MISFET, an IGBT, a SJFET, and any combination thereof.

6. The semiconductor device of claim 1, wherein the gate electrode structure of switchable cells which are arranged closer to the gate metallization has a cell layout which is different to a cell layout of the gate electrode structure of switchable cells which are arranged further away from the gate metallization.

7. The semiconductor device of claim 1, wherein each switchable cell has a specific coverage ratio defined by a ratio of the area of the gate electrode structure of said switchable cell to the total area of said switchable cell, wherein the specific coverage ratio of switchable cells which are arranged closer to the gate metallization is larger than the specific coverage ratio of switchable cells which are arranged further away from the gate metallization.

8. The semiconductor device of claim 1, wherein the gate electrode structure comprises highly doped polysilicon.

9. The semiconductor device of claim 1, wherein the gate metallization comprises at least one of a metal, a metal alloy, and a metal layer stack.

10. The semiconductor device of claim 1, wherein the gate metallization has a higher specific conductivity than the gate electrode structure.

11. The semiconductor device of claim 1, wherein the active area defined by the switchable cells comprises a third switchable region having a specific gate-drain capacitance which is different to the specific gate-drain capacitance of the first switchable region and the specific gate-drain capacitance of the second switchable region.

12. A semiconductor device, comprising:

a semiconductor substrate comprising an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim, wherein each of the switchable cells comprises a body region, a gate electrode structure and a source region;

a source metallization in ohmic contact with the source regions of the switchable cells; and

a gate metallization in ohmic contact with the gate electrode structures of the switchable cells;

wherein the active area defined by the switchable cells comprises at least a first switchable region and at least a second switchable region different to the first switchable region, wherein each switchable cell in the first switchable region and the second switchable region has a specific coverage ratio, wherein the specific coverage ratio of the switchable cells in the first switchable region is different to the specific coverage ratio of the switchable cells in the second switchable region.

13. The semiconductor device of claim 12, wherein the switchable cells in the first switchable region and the second switchable region are arranged at a given longitudinal pitch, wherein the longitudinal pitch of the switchable cells in the second switchable region is different to the longitudinal pitch of the switchable cells in the first switchable region.

14. The semiconductor device of claim 13, wherein the longitudinal pitch of the switchable cells in the second switchable region is smaller than the longitudinal pitch of the switchable cells in the first switchable region.

15. The semiconductor device of claim 12, wherein the active area defined by the switchable cells further comprises a third switchable region, wherein each switchable cell in the third switchable region has a specific coverage ratio, wherein the specific coverage ratio of the switchable cells in the third switchable region is different to the specific coverage ratio of the first switchable region and the specific coverage ratio of the second switchable region.

16. The semiconductor device of claim 12, wherein the gate metallization comprises an electrically conductive structure selected from the group consisting of a gate runner structure, a gate pad, a gate ring, a gate finger, or any combinations thereof.

17. The semiconductor device of claim 12, wherein, the gate electrode structure comprises highly doped polysilicon.