Semiconductor structure and manufacturing method of the same

• US 9,231,071 B2
• Filed: 02/24/2014
• Issued: 01/05/2016
• Est. Priority Date: 02/24/2014
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wu, Hung-Yi, Lai, Chien-Ming, Chen, Yi-Wen
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US14/187,701
• Publication Number:
  US 20150243754A1
• Time in Patent Office: 680 Days
• Field of Search: 438/658, 257/407
• US Class Current: 1/1
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Claims

1. A semiconductor structure, comprising:

an isolation layer formed on a substrate, wherein the isolation layer has a first gate trench and a second gate trench separated from the first gate trench;

a gate dielectric layer formed in the first gate trench and in the second gate trench;

a first work function metal formed on the gate dielectric layer in the first gate trench;

a first bottom barrier layer formed on the first work function metal;

a second work function metal formed on the first bottom barrier layer;

a first top barrier layer formed on the second work function metal;

a second bottom barrier layer formed on the gate dielectric layer in the second gate trench;

a third work function metal formed on the second bottom barrier layer, the third work function metal comprising the same material with that of the second work function metal; and

a second top barrier layer formed on the third work function metal;

wherein the second bottom barrier layer, the third work function metal, and the second top barrier layer cover the sidewalls of the second gate trench.

2. The semiconductor structure according to claim 1, wherein the first work function metal, the first bottom barrier layer, the second work function metal, and the first top barrier layer have U-shaped profile structures.

3. The semiconductor structure according to claim 1, wherein top surfaces of the first work function metal, the first bottom barrier layer, the second work function metal, and the first top barrier layer are coplanar and below a top surface of the isolation layer.

4. The semiconductor structure according to claim 1, wherein a ratio of a first distance between the top surface of the second work function metal and the top surface of the isolation layer to a second distance between the top surface of the second work function metal and the bottom surface of the first gate trench is 0.5-0.9.

5. The semiconductor structure according to claim 1, further comprising:

a first filling metal formed on the first top barrier layer in the first gate trench, wherein a ratio of a width of the first filling metal to a width of the first gate trench is 0.75-0.89.

6. The semiconductor structure according to claim 1, further comprising:

a second filling metal formed on the second top barrier layer in the second gate trench.

7. The semiconductor structure according to claim 1, wherein the first bottom barrier layer and the first top barrier layer independently comprise TiN, TaN, Ti/TiN, Ta/TaN, or the combinations thereof.

8. A manufacturing method of a semiconductor structure, comprising:

forming an isolation layer on a substrate, comprising forming a first gate trench and a second gate trench in the isolation layer, the second gate trench being separated from the first gate trench;

forming a gate dielectric layer in the first gate trench and in the second gate trench;

forming a first work function metal on the gate dielectric layer in the first gate trench;

forming a first bottom barrier layer on the first work function metal;

forming a second work function metal on the first bottom barrier layer;

forming a first top barrier layer on the second work function metal;

forming a second bottom barrier layer on the gate dielectric layer in the second gate trench;

forming a third work function metal on the second bottom barrier layer, the third work function metal having the same material with that of the second work function metal; and

forming a second top barrier layer on the third work function metal;

wherein the second bottom barrier layer, the third work function metal, and the second top barrier layer cover the sidewalls of the second gate trench.

9. The manufacturing method according to claim 8, wherein the first work function metal, the first bottom barrier layer, the second work function metal, and the first top barrier layer have U-shaped profile structures.

10. The manufacturing method according to claim 8, wherein top surfaces of the first work function metal, the first bottom barrier layer, the second work function metal, and the first top barrier layer are coplanar and below a top surface of the isolation layer.

11. The manufacturing method according to claim 8, wherein a ratio of a first distance between the top surface of the second work function metal and the top surface of the isolation layer to a second distance between the top surface of the second work function metal and the bottom surface of the first gate trench is 0.5-0.9.

12. The manufacturing method according to claim 8, further comprising:

forming a first filling metal on the first top barrier layer in the first gate trench, wherein a ratio of a width of the first filling metal to a width of the first gate trench is 0.75-0.89.

13. The manufacturing method according to claim 8, further comprising:

forming a second filling metal on the second top barrier layer in the second gate trench.

14. The manufacturing method according to claim 8, wherein the first bottom barrier layer and the first top barrier layer independently comprise TiN, TaN, Ti/TiN, Ta/TaN, or the combinations thereof.