Power semiconductor device having gate electrode coupling portions for etchant control

• US 9,231,082 B2
• Filed: 03/02/2015
• Issued: 01/05/2016
• Est. Priority Date: 09/27/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Sakanishi, Koichiro, Kachi, Tsuyoshi, Fujishima, Koji
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Gebreyesus, Yosef
• Application Number:
  US14/635,300
• Publication Number:
  US 20150179762A1
• Time in Patent Office: 309 Days
• Field of Search: 438/197, 438/136, 438/142, 438/151, 438/157, 438/176, 438/177, 438/184, 438/186, 438/193, 438/195, 438/260, 438/587, 438/588, 257/287, 257/691, 257/494, 257/288, 257/207, 257/E29.255, 257/E29.257, 257/E23.079, 257/E21.418, 257/E29.013
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

(a) providing a substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface being for a gate electrode and a source electrode of a MOSFET and the second main surface being for a drain region of the MOSFET;

(b) forming a gate insulating film of the MOSFET over an active cell region in which a channel of the MOSFET is formed;

(c) forming a gate wiring over the gate insulating film, the gate wiring having a plurality of gate wiring patterns arranged at a predetermined interval in a first direction and extending so as to form a stripe in a second direction intersecting the first direction in a plan view;

(d) forming a first semiconductor region of a first conductivity type in the first main surface of the semiconductor substrate, the first semiconductor region being used as the source region of the MOSFET;

(e) forming an interlayer insulating film covering the plurality of gate wiring patterns, the interlayer insulating film having an opening which exposes a part of the first semiconductor region;

(f) forming a barrier metal film over the interlayer insulating film, the barrier metal film being electrically connected to the first semiconductor region via the opening;

(g) forming a metal electrode film over the barrier metal film, the metal electrode film comprising aluminum as a principal component and being thicker than the barrier metal film; and

(h) forming the gate electrode and the source electrode of the MOSFET each comprising a laminate film of the barrier metal film and the metal electrode film by sequentially patterning the metal electrode and the barrier metal film by a selective wet etching,

wherein, in the step of (c), each of the gate wiring patterns includes a first portion located at the active region and a second portion extending to an outside region of the active region in the second direction,

wherein, in the outside region, the gate wiring includes a third portion extending perpendicular to the first direction and formed integrally with the second portion so as to connect between the second portions of the gate wiring patterns, and

wherein the selective wet etching in the step of (h) is performed outside of the gate wiring in the active region and the third portion.

2. A method of manufacturing a semiconductor device according to claim 1,

wherein, in the outside region, the gate wiring includes a fourth portion extending perpendicular to the first direction and formed integrally with the second portion so as to connect between the second portions of the gate wiring patterns, and

wherein the third portions and the fourth portions are close to each other.

3. A method of manufacturing a semiconductor device according to claim 1,

wherein the third portion is substantially linear.

4. A method of manufacturing a semiconductor device according to claim 1,

wherein the third portion has substantially the same width as that of each of the first portion and the second portion.

5. A method of manufacturing a semiconductor device according to claim 1,

wherein a width of the third portion in the second direction is wider than that of each of the first portion and the second portion.

6. A method of manufacturing a semiconductor device according to claim 1,

wherein the MOSFET is a power MOSFET.