Analog circuits having improved transistors, and methods therefor

• US 9,231,541 B2
• Filed: 09/29/2014
• Issued: 01/05/2016
• Est. Priority Date: 03/24/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Thompson, Scott E., Clark, Lawerence T.
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US14/500,236
• Publication Number:
  US 20150015334A1
• Time in Patent Office: 463 Days
• Field of Search: 330/253, 330/257, 330/277, 330/288
• US Class Current: 1/1
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2203/45344 At least one of the AAC sub-circuits being a current mirror
• CPC Class Codes: H03F 2203/45454 the CSC comprising biasing means controlled by the input signal
• CPC Class Codes: H03F 2203/45506 the CSC comprising only one switch
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 2203/45676 the LC comprising one cascode current mirror
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: H03F 3/45071 with semiconductor devices only
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45273 Mirror types

Abstract

Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.

Claims

1. A circuit, comprising:

a plurality of transistors having controllable current paths coupled between at least a first node and a second node, the transistors configured to generate an analog electrical output signal in response to an analog input value;

wherein

at least one of the transistors operates with an applied body bias, and has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a doped screen layer formed over a doped body region, with the doped screen layer extending between and in contact with a source and a drain.

2. The circuit of claim 1, wherein:

the plurality of transistors includes a current mirror circuit comprising a reference transistor with a gate coupled to its drain and configured to pass an input reference current, and

a mirror transistor with a gate coupled to the gate of the reference transistor to generate an output current that tracks the input reference current, wherein at least the mirror transistor includes the deeply depleted channel.

3. The circuit of claim 2, wherein:

the reference transistor is selected from;

a transistor having the deeply depleted channel, and

a transistor having a doped channel formed below its gate.

4. The circuit of claim 1, wherein the plurality of transistors includes at least one first biased transistor and at least one second biased transistor, the first biased transistor having a body coupled to receive a standard bias voltage, the second biased transistor having a body coupled to receive a forward bias voltage that lowers the threshold voltage of the second biased transistor with respect to the first biased transistor.

5. The circuit of claim 4, wherein at least the second biased transistor includes the deeply depleted channel.

6. The circuit of claim 1, wherein the plurality of transistors includes a differential pair of transistors, comprising:

a first transistor having a gate coupled to receive a first input signal and a source coupled to a bias node, and

a second transistor having a gate coupled to receive a second input signal and a source coupled to the bias node, wherein the first and second transistors are matching transistors that both include a deeply depleted channel.

7. The circuit of claim 6, wherein the circuit further comprises:

a differential amplifier circuit comprising the differential pair of transistors; and

a biasing circuit coupled to the bias node that limits a current flow through the differential pair of transistors.

8. The circuit of claim 7, wherein the biasing circuit includes at least one bias transistor having a source-drain path coupled between the bias node and a power supply node, and a gate coupled to receive a bias control signal.

9. The circuit of claim 8, wherein the plurality of transistors includes standard biased transistors of a first conductivity type having bodies coupled to a standard body bias voltage;

and

wherein the at least one bias transistor is of the first conductivity type and has a body coupled to a forward bias body voltage different from the standard body bias voltage, the forward body bias voltage lowering the threshold voltage of the bias transistor with respect to the standard biased transistors.

10. The circuit of claim 8, wherein the plurality of transistors includes standard threshold voltage (Vt) transistors of a first conductivity type;

and

wherein the at least one bias transistor is a low Vt transistor of the first conductivity type, having a lower threshold voltage than the standard Vt transistors.

11. The circuit of claim 7, wherein the differential amplifier circuit further includes a current mirror load circuit coupled to the drains of the differential pair of transistors, the current mirror circuit comprising:

a first load transistor having a source coupled to a first power supply node, a gate coupled to its drain, and a drain coupled to the drain of the first transistor of the differential pair, and

a second load transistor having a source coupled to the first power supply node and a gate coupled to the gate of the first load transistor, and a drain coupled to the drain of the second transistor of the differential pair;

wherein the first and second load transistors have deeply depleted channels and are of an opposite conductivity type than the differential pair of transistors.

12. The circuit of claim 6, wherein the circuit further comprises:

an analog comparator comprising the differential pair of transistors; and

an enable circuit configured to enable and disable a current path between the bias node and a first power supply node in response to an enable signal.

13. The circuit of claim 12, wherein the plurality of transistors includes standard threshold voltage (Vt) transistors of a first conductivity type;

and

wherein the enable circuit includes at least one enable transistor having a source-drain path coupled between the bias node and a power supply node, and a gate coupled to receive the enable signal, the enable transistor being a low Vt transistor of the first conductivity type having a lower threshold voltage than the standard Vt transistors.

14. The circuit of claim 12, wherein the analog comparator circuit further includes:

a first driver transistor having a source coupled to a second power supply node, a gate coupled to a drain of the first transistor of the differential pair, and a drain coupled to the drain of the second transistor of the differential pair; and

a second driver transistor having a source coupled to the second power supply node, a gate coupled to a drain of the second transistor of the differential pair, and a drain coupled to the drain of the first transistor of the differential pair;

wherein the first and second driver transistors each have deeply depleted channel and are of an opposite conductivity type than the differential pair of transistors.

15. The circuit of claim 6, wherein the circuit comprises an operational amplifier comprising:

a noninverting input coupled to a gate of the first transistor of the differential pair; and

an inverting input coupled to a gate of the second transistor of the differential pair.

16. A circuit, comprising:

a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value;

wherein at least one of the transistors operates with an applied body bias and has a deeply depleted channel formed below its gate that includes a Vt set layer formed between a substantially undoped channel region and a doped screen layer formed over a doped body region, with both the Vt set layer and the doped screen layer extending between and in contact with a source and a drain.

17. The circuit of claim 16, wherein:

the plurality of transistors includes a current mirror circuit comprising a reference transistor with a gate coupled to its drain and configured to pass an input reference current; and

a mirror transistor with a gate coupled to the gate of the reference transistor to generate an output current that tracks the input reference current;

wherein at least the mirror transistor includes the deeply depleted channel.

18. The circuit of claim 16, wherein the plurality of transistors includes at least one first biased transistor and at least one second biased transistor, the first biased transistor having a body coupled to receive a standard bias voltage, the second biased transistor having a body coupled to receive a forward bias voltage that lowers the threshold voltage of the second biased transistor with respect to the first biased transistor.

19. The circuit of claim 16, wherein the plurality of transistors includes a differential pair of transistors, comprising:

a first transistor having a gate coupled to receive a first input signal and a source coupled to a bias node; and

a second transistor having a gate coupled to receive a second input signal and a source coupled to the bias node, wherein the first and second transistors are matching transistors that both include a deeply depleted channel.

20. The circuit of claim 16, wherein the circuit comprises an operational amplifier comprising:

a noninverting input coupled to a gate of a first transistor of a differential pair, and

an inverting input coupled to a gate of a second transistor of a differential pair.