Techniques relating to phase-locked loop circuits

• US 9,231,601 B1
• Filed: 01/09/2015
• Issued: 01/05/2016
• Est. Priority Date: 01/09/2015
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Oh, Kyung Suk, Lee, Hae-Chang, Ahn, Heetae
• Primary Examiner(s): Houston, Adam
• Application Number:
  US14/593,940
• Time in Patent Office: 361 Days
• Field of Search: 327147-149, 327156-158
• US Class Current: 1/1
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

A phase-locked loop circuit includes a regulator circuit, first and second inductor-capacitor tank circuits, and first and second load capacitors. The regulator circuit generates a supply voltage. The first load capacitor is coupled to the regulator circuit and to the first inductor-capacitor tank circuit. The first load capacitor provides current for the supply voltage to the first inductor-capacitor tank circuit. The second load capacitor is coupled to the regulator circuit and to the second inductor-capacitor tank circuit. The second load capacitor provides current for the supply voltage to the second inductor-capacitor tank circuit.

Claims

1. A phase-locked loop circuit comprising:

a regulator circuit to generate a supply voltage;

first and second inductor-capacitor tank circuits;

a first load capacitor coupled to the regulator circuit and to the first inductor-capacitor tank circuit, wherein the first load capacitor provides current for the supply voltage to the first inductor-capacitor tank circuit; and

a second load capacitor coupled to the regulator circuit and to the second inductor-capacitor tank circuit, wherein the second load capacitor provides current for the supply voltage to the second inductor-capacitor tank circuit.

2. The phase-locked loop circuit of claim 1, wherein each of the first and the second inductor-capacitor tank circuits is part of an oscillator circuit in the phase-locked loop circuit.

3. The phase-locked loop circuit of claim 1, further comprising:

a third inductor-capacitor tank circuit; and

a third load capacitor coupled to the regulator circuit and to the third inductor-capacitor tank circuit, wherein the third load capacitor provides current for the supply voltage to the third inductor-capacitor tank circuit.

4. The phase-locked loop circuit of claim 3, further comprising:

a supply voltage delivery circuit that comprises a delivery inductance and the third load capacitor, wherein a resonant frequency of the delivery inductance and the third load capacitor is within 30% of a frequency of a periodic signal generated by the third inductor-capacitor tank circuit.

5. The phase-locked loop circuit of claim 1, further comprising:

a supply voltage delivery circuit that comprises a first delivery inductance and the first load capacitor, wherein a resonant frequency of the first delivery inductance and the first load capacitor is substantially equal to a frequency of a periodic signal generated by the first inductor-capacitor tank circuit.

6. The phase-locked loop circuit of claim 5, wherein the supply voltage delivery circuit further comprises a second delivery inductance and the second load capacitor, and wherein a resonant frequency of the second delivery inductance and the second load capacitor is substantially equal to a frequency of a periodic signal generated by the second inductor-capacitor tank circuit.

7. A method for manufacturing an integrated circuit comprising:

providing a first regulator circuit to generate a first supply voltage;

providing a first inductor-capacitor tank circuit in a first oscillator circuit in a first phase-locked loop circuit in the integrated circuit;

providing a first supply voltage delivery circuit comprising a first load capacitor and a first delivery inductance to provide the first supply voltage to the first oscillator circuit; and

selecting a capacitance for the first load capacitor to cause a resonant frequency of the first load capacitor and the first delivery inductance to be closer to an operating frequency of a first clock signal to be generated by the first inductor-capacitor tank circuit to reduce noise in the first supply voltage delivery circuit.

8. The method of claim 7, further comprising:

providing a second regulator circuit to generate a second supply voltage;

providing a second inductor-capacitor tank circuit in a second oscillator circuit in a second phase-locked loop circuit in the integrated circuit;

providing a second supply voltage delivery circuit comprising a second load capacitor and a second delivery inductance to provide the second supply voltage to the second oscillator circuit, wherein the first and the second supply voltage delivery circuits are coupled to a substrate in the integrated circuit; and

selecting a capacitance for the second load capacitor to cause a resonant frequency of the second load capacitor and the second delivery inductance to be closer to an operating frequency of a second clock signal to be generated by the second inductor-capacitor tank circuit to reduce cross-coupling of noise through the substrate between the first and the second supply voltage delivery circuits.

9. The method of claim 7, further comprising:

providing a second inductor-capacitor tank circuit in the first phase-locked loop circuit, wherein the first supply voltage delivery circuit comprises a second load capacitor and a second delivery inductance to provide the first supply voltage to the second inductor-capacitor tank circuit; and

selecting a capacitance for the second load capacitor to cause a resonant frequency of the second load capacitor and the second delivery inductance to be closer to an operating frequency of a second clock signal to be generated by the second inductor-capacitor tank circuit to reduce noise in the first supply voltage delivery circuit.

10. The method of claim 9, further comprising:

providing a second regulator circuit to generate a second supply voltage;

providing a third inductor-capacitor tank circuit in a second oscillator circuit in a second phase-locked loop circuit in the integrated circuit;

providing a second supply voltage delivery circuit comprising a third load capacitor and a third delivery inductance to provide the second supply voltage to the second oscillator circuit, wherein the first and the second supply voltage delivery circuits are coupled to a substrate in the integrated circuit; and

selecting a capacitance for the third load capacitor to cause a resonant frequency of the third load capacitor and the third delivery inductance to be closer to an operating frequency of a third clock signal to be generated by the third inductor-capacitor tank circuit to reduce cross-coupling of noise through the substrate between the first and the second supply voltage delivery circuits.

11. The method of claim 10, further comprising:

providing a fourth inductor-capacitor tank circuit in the second phase-locked loop circuit, wherein the second supply voltage delivery circuit comprises a fourth load capacitor and a fourth delivery inductance to provide the second supply voltage to the fourth inductor-capacitor tank circuit; and

selecting a capacitance for the fourth load capacitor to cause a resonant frequency of the fourth load capacitor and the fourth delivery inductance to be closer to an operating frequency of a fourth clock signal to be generated by the fourth inductor-capacitor tank circuit to reduce noise in the second supply voltage delivery circuit.

12. The method of claim 9, wherein the first supply voltage delivery circuit further comprises a third delivery inductance coupled between the first inductor-capacitor tank circuit and a node at a ground voltage, and wherein the first supply voltage delivery circuit further comprises a fourth delivery inductance coupled between the second inductor-capacitor tank circuit and the third delivery inductance.

13. The method of claim 9, wherein selecting a capacitance for the first load capacitor and selecting a capacitance for the second load capacitor further comprise distributing a loading capacitance for the first regulator circuit between the first and the second load capacitors to reduce the first and the second delivery inductances.

14. The method of claim 9, wherein providing a first inductor-capacitor tank circuit and providing a second inductor-capacitor tank circuit further comprise placing the first inductor-capacitor tank circuit closer to the first regulator circuit than the second inductor-capacitor tank circuit, and wherein the first inductor-capacitor tank circuit generates a frequency range for the first clock signal that is greater than a frequency range that the second inductor-capacitor tank circuit generates for the second clock signal.

15. A method for operating a phase-locked loop circuit comprising:

generating a supply voltage using a regulator circuit;

generating a first clock signal using a first inductor-capacitor tank circuit in a first mode of operation of the phase-locked loop circuit;

generating a second clock signal using a second inductor-capacitor tank circuit in a second mode of operation of the phase-locked loop circuit;

providing current for the supply voltage to the first inductor-capacitor tank circuit using a first load capacitor coupled to the first inductor-capacitor tank circuit; and

providing current for the supply voltage to the second inductor-capacitor tank circuit using a second load capacitor coupled to the second inductor-capacitor tank circuit.

16. The method of claim 15, wherein each of the first and the second load capacitors has substantially a same capacitance.

17. The method of claim 15, further comprising:

generating a third clock signal using a third inductor-capacitor tank circuit in a third mode of operation of the phase-locked loop circuit; and

providing current for the supply voltage to the third inductor-capacitor tank circuit using a third load capacitor coupled to the third inductor-capacitor tank circuit.

18. The method of claim 17, wherein each of the first, the second, and the third inductor-capacitor tank circuits is part of a same oscillator circuit in the phase-locked loop circuit.

19. The method of claim 15, wherein providing current for the supply voltage to the first inductor-capacitor tank circuit using a first load capacitor comprises providing the current for the supply voltage to the first inductor-capacitor tank circuit using a supply voltage delivery circuit that comprises a first delivery inductance and the first load capacitor, and wherein a resonant frequency of the first delivery inductance and the first load capacitor is substantially equal to a frequency of the first clock signal generated by the first inductor-capacitor tank circuit.

20. The method of claim 19, wherein providing current for the supply voltage to the second inductor-capacitor tank circuit using a second load capacitor comprises providing the current for the supply voltage to the second inductor-capacitor tank circuit using the supply voltage delivery circuit that further comprises a second delivery inductance and the second load capacitor, and wherein a resonant frequency of the second delivery inductance and the second load capacitor is substantially equal to a frequency of the second clock signal generated by the second inductor-capacitor tank circuit.