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System and architecture for secure computer devices

  • US 9,231,921 B2
  • Filed: 08/20/2013
  • Issued: 01/05/2016
  • Est. Priority Date: 08/20/2013
  • Status: Active Grant
First Claim
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1. A secure computer comprising:

  • a plurality of peripheral subsystems for receiving, storing, retrieving from storage and outputting data;

    a host system running an operating system and applications that receive, store, retrieve and output the data, the host system including a system bus and an interface for connecting the host system to an expansion bus that is separate and independent from the system bus, the expansion bus being one of a Peripheral Component Interconnect (PCI) and a PCI Express (PCIe) expansion bus;

    a secure subsystem that controls access by the host system to the plurality of peripheral subsystems for receiving, storing, retrieving and outputting the data; and

    a secure connection between the expansion bus interface of the host system and the secure subsystem that connects the plurality of peripheral subsystems to the host system.

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