Unit pixels configured to output different pixel signals through different lines and image sensors including the same

• US 9,232,161 B2
• Filed: 03/12/2014
• Issued: 01/05/2016
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Suh, Sung-Ho, Yoo, Kwi-Sung, Lim, Seung-Hyun, Ham, Seog-Heon, Lee, Kang-Sun
• Primary Examiner(s): Selby, Gevell
• Application Number:
  US14/206,126
• Publication Number:
  US 20140267861A1
• Time in Patent Office: 664 Days
• Field of Search: 348/308
• US Class Current: 1/1
• CPC Class Codes: H04N 25/134 based on three different wavelength filter elements
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

An image sensor includes a pixel array and a plurality of pairs of column lines. The pixel array includes a plurality of unit pixel areas arranged in a plurality of rows and columns. Each of the unit pixel areas includes a readout circuit connected to a corresponding pair of column lines, and first and second photo-electric conversion devices sharing the readout circuit. Each of the unit pixel areas is configured to output a first pixel signal corresponding to a photoelectron generated by the first photo-electric conversion device through the first column line, and to output a second pixel signal corresponding to a photoelectron generated by the second photo-electric conversion device through the second column line.

Claims

1. An image sensor comprising:

a pixel array including a plurality of unit pixel areas arranged in a plurality of rows and columns; and

a plurality of pairs of column lines, each pair of column lines being aligned with a column among the plurality of columns,

wherein each of the plurality of unit pixel areas includes,

a readout circuit connected to a corresponding pair of column lines, and

first and second photo-electric conversion devices sharing the readout circuit; and

wherein each of the plurality of unit pixel areas is configured to,

output, through a first column line among the corresponding pair of column lines, a first pixel signal corresponding to a first photoelectron generated by the first photo-electric conversion device, and

output, through a second column line among the corresponding pair of column lines, a second pixel signal corresponding to a second photoelectron generated by the second photo-electric conversion device.

2. The image sensor of claim 1, wherein the first photoelectron corresponds to a first color, and the second photoelectron corresponds to a second color, which is different from the first color.

3. The image sensor of claim 2, wherein each readout circuit aligned in an odd row among the plurality of rows is configured to output the first pixel signal through the first column line in response to an odd readout signal, and each readout circuit aligned in an even row among the plurality of rows is configured to output the second pixel signal through the second column line in response to the odd readout signal.

4. The image sensor of claim 2, wherein each readout circuit aligned in an even row among the plurality of rows is configured to output the first pixel signal through the first column line in response to an even readout signal, and each readout circuit aligned in an odd row among the plurality of rows is configured to output the second pixel signal through the second column line in response to the even readout signal.

5. The image sensor of claim 2, wherein each unit pixel area aligned in an odd row among the plurality of rows comprises:

a first charge transmit transistor configured to transmit a photo charge generated by the first photo-electric conversion device to a shared node when an odd readout operation is performed; and

a second charge transmit transistor configured to transmit a photo charge generated by the second photo-electric conversion device to the shared node when an even readout operation is performed.

6. The image sensor of claim 5, wherein the readout circuit included in each unit pixel area aligned in the odd row among the plurality of rows comprises:

a reset transistor configured to reset the shared node with a supply voltage in response to a reset signal;

a drive transistor configured to drive an output node based on quantity of charges at the shared node;

a first select transistor configured to connect the output node to the first column line in response to an odd readout signal; and

a second select transistor configured to connect the output node to the second column line in response to an even readout signal.

7. The image sensor of claim 2, wherein each unit pixel area aligned in an even row among the plurality of rows comprises:

a first charge transmit transistor configured to transmit a photo charge generated by the first photo-electric conversion device to a shared node when an even readout operation is performed; and

a second charge transmit transistor configured to transmit a photo charge generated by the second photo-electric conversion device to the shared node when an odd readout operation is performed.

8. The image sensor of claim 7, wherein the readout circuit included in each unit pixel area aligned in the even row among the plurality of rows comprises:

a reset transistor configured to reset the shared node with a supply voltage in response to a reset signal;

a drive transistor configured to drive an output node based on quantity of charges at the shared node;

a third select transistor configured to connect the output node to the first column line in response to an even readout signal; and

a fourth select transistor configured to connect the output node to the second column line in response to an odd readout signal.

9. A unit pixel having a shared pixel structure, the unit pixel comprising:

a first photo-electric conversion device configured to generate a first pixel signal corresponding to a first color;

a second photo-electric conversion device configured to generate a second pixel signal corresponding to a second color, which is different from the first color; and

a readout circuit connected to the first and second photo-electric devices, the readout circuit being configured to output the first pixel signal and the second pixel signal via different column lines.

10. The unit pixel of claim 9, wherein the first and second photo-electric conversion devices share the readout circuit.

11. The unit pixel of claim 9, wherein the unit pixel includes only a single readout circuit.

12. An image sensor comprising:

a pixel array including a plurality of unit pixels arranged in a plurality of rows and columns, each of the plurality of unit pixels having a shared pixel structure, and each of the plurality of unit pixels including

a first photo-electric conversion device configured to generate a first pixel signal corresponding to a first color,

a second photo-electric conversion device configured to generate a second pixel signal corresponding to a second color, which is different from the first color, and

a readout circuit connected to the first and second photo-electric devices, the readout circuit being configured to output the first pixel signal and the second pixel signal via different column lines;

a plurality of pairs of column lines, each pair of column lines being aligned with a column among the plurality of columns; and

wherein the readout circuit is configured to output the first pixel signal via the first column line among a corresponding pair of column lines, and to output the second pixel signal via the second column line among the corresponding pair of column lines.

13. The image sensor of claim 12, wherein the readout circuit is configured to output the first pixel signal only via the first column line, and to output the second pixel signal only via the second column line.