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Load reduced memory module

  • US 9,232,651 B2
  • Filed: 04/15/2015
  • Issued: 01/05/2016
  • Est. Priority Date: 10/15/2013
  • Status: Active Grant
First Claim
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1. A motherboard substrate comprising:

  • first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal;

    a processor socket connected to the first set of data lines;

    a first slot connected to the processor socket via a first subset of the first set of nibbles; and

    a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles, wherein the first subset of the first set of nibbles does not connect to the second slot, and wherein the second subset of the first set of nibbles does not connect to the first slot.

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