Load reduced memory module

• US 9,232,651 B2
• Filed: 04/15/2015
• Issued: 01/05/2016
• Est. Priority Date: 10/15/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Rajan, Suresh
• Primary Examiner(s): Thompson, Timothy
• Assistant Examiner(s): McAllister, Michael F
• Application Number:
  US14/687,687
• Publication Number:
  US 20150223333A1
• Time in Patent Office: 265 Days
• Field of Search: 174/261
• US Class Current: 1/1
• CPC Class Codes: G06F 1/184 Mounting of motherboards
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7803 System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H05K 1/11 Printed elements for providing electric connections to or between printed circuits
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: H05K 2201/10189 Non-printed connector

Abstract

The embodiments described herein describe technologies for memory systems. One implementation of a motherboard substrate includes first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal. The motherboard substrate also includes a processor socket connected to the first set of data lines, a first slot connected to the processor socket via a first subset of the first set of nibbles, and a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles.

Claims

1. A motherboard substrate comprising:

first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal;

a processor socket connected to the first set of data lines;

a first slot connected to the processor socket via a first subset of the first set of nibbles; and

a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles, wherein the first subset of the first set of nibbles does not connect to the second slot, and wherein the second subset of the first set of nibbles does not connect to the first slot.

2. The motherboard substrate of claim 1, wherein the first subset of the first set of nibbles does not overlap with the second subset of the first set of nibbles.

3. The motherboard substrate of claim 1, wherein the second set of data lines does not connect to the processor socket.

4. The motherboard substrate of claim 1, wherein each of the first set of nibbles includes a respective four of the first set of data lines, and wherein each of the second set of nibbles includes a respective four of the second set of data lines.

5. The motherboard substrate of claim 4, wherein the first set of data lines includes seventy two data lines.

6. The motherboard substrate of claim 5, wherein the second set of data lines includes thirty six data lines.

7. The motherboard substrate of claim 1, wherein the first subset of the first set of nibbles are interleaved with the second subset of the first set of nibbles.

8. The motherboard substrate of claim 1, wherein the first subset of the first set of nibbles connect to the same relative locations on the first slot as the second subset of the first set of nibbles on the second slot.

9. The motherboard substrate of claim 1, wherein the second set of nibbles connect to the same relative locations on the first and the second slots, respectively.

10. A printed circuit board comprising:

a processor socket having a first set of even nibble connections connected to a first set of nibbles and a second set of odd nibble connections connected to a second set of nibbles;

a first module socket having a second set of even nibble connections connected to the first set of nibbles and a second set of odd nibble connections connected to a third set of nibbles; and

a second module socket having a third set of even nibble connections connected to the second set of nibbles and a third set of odd nibble connections connected to the third set of nibbles,

wherein each nibble in each of the first, the second, and the third sets of nibbles includes a respective plurality of wires for timing signals.

11. The printed circuit board of claim 10, wherein each nibble in each of the first, the second, and the third sets of nibbles includes a respective plurality of wires for data signals.

12. The printed circuit board of claim 11, wherein a total number of the plurality of wires for data signals from the first and the second sets of nibbles is seventy two.

13. The printed circuit board of claim 12, wherein a total number of the plurality of wires for timing signals in the first and the second sets of nibbles is thirty six.

14. The printed circuit board of claim 12, wherein a total number of the plurality of wires for data signals from the third set of nibbles is thirty six.

15. The printed circuit board of claim 14, wherein a total number of the plurality of wires for timing signals from the third set of nibbles is eighteen.

16. A motherboard substrate comprising:

first and second sets of data lines, the first set of data lines including seventy two data lines arranged into a first set of eighteen nibbles and the second set of data lines including thirty six data lines arranged into a second set of nine nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal;

a processor socket connected to the first set of data lines but not the second set of data lines;

a first slot connected to the processor socket via a first subset of nine of the first set of eighteen nibbles but not via a second subset of nine of the first set eighteen of nibbles, the first subset being mutually exclusive with the second subset; and

a second slot connected to the processor socket via the second subset of nine of the first set of eighteen nibbles but not via the first subset of nine of the first set of eighteen nibbles and connected to the first slot via the second set of nibbles but not via the first set of nibbles.

17. The motherboard substrate of claim 16, wherein the first subset of nine of the first set of eighteen nibbles are interleaved with the second subset of nine of the first set of eighteen nibbles.

18. The motherboard substrate of claim 16, wherein the first subset of nine of the first set of eighteen nibbles connect to the same relative locations on the first slot as the second subset of nine of the first set of eighteen nibbles on the second slot.

19. The motherboard substrate of claim 16, wherein the second set of nine nibbles connect to the same relative locations on the first and the second slots, respectively.

20. A motherboard substrate comprising:

first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal;

a processor socket connected to the first set of data lines;

a first slot connected to the processor socket via a first subset of the first set of nibbles; and

a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles, wherein each of the first set of nibbles includes a respective four of the first set of data lines, wherein each of the second set of nibbles includes a respective four of the second set of data lines, and wherein the first set of data lines includes seventy two data lines, and wherein the first set of data lines includes seventy two data lines.

21. The motherboard substrate of claim 20, wherein the second set of data lines includes thirty six data lines.

22. A motherboard substrate comprising:

first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal;

a processor socket connected to the first set of data lines;

a first slot connected to the processor socket via a first subset of the first set of nibbles; and

a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles, wherein the first subset of the first set of nibbles connect to the same relative locations on the first slot as the second subset of the first set of nibbles on the second slot.

23. A motherboard substrate comprising:

first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal;

a processor socket connected to the first set of data lines;

a first slot connected to the processor socket via a first subset of the first set of nibbles; and

a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles, wherein the second set of nibbles connect to the same relative locations on the first and the second slots, respectively.