High performance electrical circuit structure

• US 9,232,654 B2
• Filed: 10/18/2011
• Issued: 01/05/2016
• Est. Priority Date: 06/02/2009
• Status: Active Grant

• Current Assignee: LCP Medical Technologies Incorporated
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Oh, Jaehwan
• Application Number:
  US13/879,783
• Publication Number:
  US 20130223034A1
• Time in Patent Office: 1,540 Days
• Field of Search: 257/737, 257/E23.067, 257/758, 257/528, 257/779, 438/107, 438/612, 438/622, 438/106, 438/109, 438/667
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H05K 1/0274 Optical details, e.g. printed circuits comprising integral optical means H05K1/0269 takes precedence; coupling light guides with opto-electronic components G02B6/42
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/16 incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• CPC Class Codes: H05K 1/18 Printed circuits structurally associated with non-printed electric components H05K1/0201, H05K1/023, H05K1/0243, and H05K1/16 take precedence
• CPC Class Codes: H05K 2201/0133 Elastomeric or compliant polymer elastomeric conductor H05K2201/0314
• CPC Class Codes: H05K 3/1291 Firing or sintering at relative high temperatures for patterns on inorganic boards, e.g. co-firing of circuits on green ceramic sheets
• CPC Class Codes: H05K 3/30 Assembling printed circuits with electric components, e.g. with resistor
• CPC Class Codes: H05K 3/325 by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor adaptations of leads inserted in holes for press-fit connections H05K3/308
• CPC Class Codes: H05K 3/4007 Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/4664 Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders H05K3/4647 takes precedence
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A high performance electrical interconnect adapted to provide an interface between terminals on first and second circuit members. The electrical interconnect includes a first circuitry layer with a first surface and a second surface having a plurality of contact pads adapted to electrically coupled with the terminals on the first circuit member. At least one dielectric layer is printed on the first surface of the first circuitry layer. The dielectric layer includes a plurality recesses. A conductive material is deposited in at least a portion of the recesses to create circuit geometry electrically coupled with the first circuitry layer. A second circuitry layer includes a first surface a plurality of contact pads adapted to electrically couple with the terminals on the second circuit member and a second surface attached to the dielectric layers. The circuit geometry electrically couples the first circuitry layer to the second circuitry layer.

Claims

1. A high performance electrical interconnect adapted to provide an interface between terminals on first and second circuit members, the electrical interconnect comprising:

a first circuitry layer comprising a first surface and a second surface with a plurality of contact pads adapted to electrically coupled with the terminals on the first circuit member;

at least one dielectric layer printed on the first surface of the first circuitry layer, the dielectric layer comprising a plurality recesses, the dielectric layer comprising a compliant material located behind contact pads, the compliance of the compliant material biasing the contact pads toward the terminals on at least one of the first or second circuit members;

a conductive material deposited in at least a portion of the recesses comprising circuit geometry electrically coupled with the first circuitry layer; and

a second circuitry layer comprising a first surface a plurality of contact pads adapted to electrically coupled with the terminals on the second circuit member and a second surface attached to the dielectric layers, the circuit geometry electrically coupling the first circuitry layer to the second circuitry layer.

2. The high performance electrical interconnect of claim 1 comprising a conduct plating layer on at least a portion of the circuit geometry.

3. The high performance electrical interconnect of claim 1 comprising at least one printed electrical device located on a dielectric layer and electrically coupled to at least a portion of the circuit geometry.

4. The high performance electrical interconnect of claim 3 wherein the electrical device is selected from one of shielding, near device decoupling, capacitors, transistors, resistors, filters, signal or power altering and enhancing devices, memory devices, embedded IC devices, RF antennae, and the like.

5. The high performance electrical interconnect of claim 1 comprising an optical quality material deposited in at least a portion of the recesses comprising one or more optical circuit geometries.

6. The high performance electrical interconnect of claim 1 comprising one or more optical fibers located in at least a portion of the recesses comprising one or more optical circuit geometries.

7. The high performance electrical interconnect of claim 1 wherein at least a portion of the circuit geometry comprises a via electrically coupling the first circuitry layer to the second circuitry layer.

8. The high performance electrical interconnect of claim 1 comprising one or more contact members electrically coupled to at least a portion of the circuit geometry and extending above the dielectric covering layer.

9. The high performance electrical interconnect of claim 1 wherein the recesses in the circuit geometry comprise substantially rectangular cross-sectional shapes.

10. An edge connector on the high performance electrical interconnect of claim 1 comprising:

a first portion of the circuit geometry extending beyond the dielectric covering layer;

a compliant material located along a surface of the first portion of the circuit geometry; and

a second portion of the circuit geometry located on top of the compliant material.

11. The high performance electrical interconnect of claim 1 comprising a socket housing coupled to the electrical interconnect, the contact pads on the second circuitry layer positioned in a socket housing recess that is sized to receive the second circuit member.

12. The high performance electrical interconnect of claim 1 wherein the dielectric layers comprise at least one additional circuitry plane selected from one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, or a flexible circuit.

13. The high performance electrical interconnect of claim 1 comprising:

at least one dielectric covering layer on the second surface of the first circuitry layer; and

a plurality of openings in the dielectric covering layer providing access to the contact pads on the first circuitry layer.

14. The high performance electrical interconnect of claim 1 wherein the first circuitry layer comprises:

at least one printed dielectric layer comprising a plurality recesses; and

a conductive material deposited in at least a portion of the recesses comprising via structures electrically coupled with the first circuitry layer.

15. An high performance electrical interconnect assembly comprising:

a housing retaining the high performance electrical interconnect of claim 1;

a first circuit member comprising electrical terminals compressively engaged with the contact pads on the first circuitry layer; and

a second circuit member comprising electrical terminals compressively engaged with the contact pads on the second circuitry layer.

16. The electrical interconnect assembly of claim 15 wherein the first and second circuit members are selected from one of a dielectric layer, a printed circuit board, a flexible circuit, a bare die device, an integrated circuit device, organic or inorganic substrates, or a rigid circuit.