Method and apparatus reduced switch-on rate low dropout regulator (LDO) bias and compensation

• US 9,235,225 B2
• Filed: 03/07/2013
• Issued: 01/12/2016
• Est. Priority Date: 11/06/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Price, Burt L., Kolla, Yeshwant Nagaraj, Shah, Dhaval R.
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): NASH, GARY A
• Application Number:
  US13/788,115
• Publication Number:
  US 20140125300A1
• Time in Patent Office: 1,041 Days
• Field of Search: 323/274, 323/280, 323/284, 323/289, 323/315, 323/316, 327 50- 52, 327/54, 327/56, 327/77, 327/80, 327/89, 361/13, 361/18
• US Class Current: 1/1
• CPC Class Codes: G05F 1/468 characterised by reference voltage circuitry, e.g. soft start, remote shutdown
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A switchable bias current biases, in an operational state, a differential amplifier with a full-slew bias current. A system on/off signal transitions from an operational state to a power-down state. The transition disables the differential amplifier and switches the switchable bias current to a reduced slew bias current. The system on/off signal transitions from the power-down state to the operational state, the differential amplifier is enabled, and the switchable bias current is delayed, by a reduced slew duration, from switching to the full-slew bias current. The enabled differential amplifier slews toward a reference voltage at a reduced slew rate caused by the reduced slew bias current. The switchable bias current, after the reduced slew duration, switches to the full-slew bias current. Optionally, a regulated pass gate is disabled in response to the system on/off signal transitioning from the operational state to the power-down state.

Claims

1. A reduced switch-on slew low dropout (LDO) regulator, further comprising:

a pass gate, configured to controllably couple a voltage rail to a regulator output, the control being based in part on a pass gate control signal;

a controllable slew differential amplifier, switchable between a slew-limiting state and a full-slew state, the controllable slew differential amplifier being configured to receive a feedback from the regulator output, and to generate the pass gate control signal, based on a reference voltage and the feedback, at a full-slew rate in the full-slew state, and at a reduced slew rate in the slew-limiting state;

a pass gate disabling circuit, configured to selectively over-ride the pass gate control signal and switch the pass gate OFF;

a switchable tail current source, coupled to the controllable slew differential amplifier, configured as switchable between sourcing a slew-limiting bias current and sourcing a full-slew bias current, and comprising a switchable full-slew bias current source and a slew-limiting bias current source, the switchable full-slew bias current source being configured to source the full-slew bias current when ON, the slew-limiting bias current source being in parallel with the switchable full-slew bias current source and configured to source the slew-limiting bias current; and

a tail current control circuit, configured to switch OFF the switchable full-slew bias current source in response to an ON-to-OFF transition of a system ON-OFF signal (ST_ON/OFF) and, at a delay DLY after an OFF-to-ON transition of ST_ON/OFF, to switch ON the switchable full-slew bias current source.

2. The reduced switch-on slew LDO regulator of claim 1, wherein the LDO regulator is configured to generate the pass gate control signal at the full-slew rate when biasing a transistor with the full-slew bias current, and at the reduced slew rate when biasing the transistor with the slew-limiting bias current.

3. A The reduced switch-on slew low-dropout (LDO) regulator, further comprising

a pass gate, configured to controllably couple a voltage rail to a regulator output, the control being based in part on a pass gate control signal;

a controllable slew differential amplifier, switchable between a slew-limiting state and a full-slew state, the controllable slew differential amplifier being configured to receive a feedback from the regulator output, and to generate the pass gate control signal, based on a reference voltage and the feedback, at a full-slew rate in the full-slew state, and at a reduced slew rate in the slew-limiting state;

a pass gate disabling circuit, configured to selectively over-ride the pass gate control signal and switch the pass gate OFF;

a switchable tail current source, coupled to the controllable slew differential amplifier, and configured as switchable between sourcing a slew-limiting bias current and sourcing a full-slew bias current; and

a tail current control circuit, configured to switch the switchable tail current source to the slew-limiting bias current in response to an ON-to-OFF transition of a system ON-OFF signal (ST_ON/OFF) and, at a delay (DLY) after an OFF-to-ON transition of ST_ON/OFF, to switch the switchable tail current source from the slew-limiting bias current to the full-slew bias current.

4. The reduced switch-on slew LDO regulator of claim 3, wherein the controllable slew differential amplifier is further configured to slew, in response to the OFF-to-ON transition of ST_ON/OFF, from an initial zero voltage to approximately Vref, at a slew rate slewing from the initial zero voltage to approximately Vref in a time duration approximately equal to DLY.

5. The reduced switch-on slew LDO regulator of claim 4, wherein the tail current control circuit includes a delay capacitor, and a charging circuit, the charging circuit being configured to charge the delay capacitor in response to the OFF-to-ON transition of ST_ON/OFF, from a zero voltage to a tail current source mode switch threshold, in a charging time having a duration approximately equal to DLY.

6. The reduced switch-on slew LDO regulator of claim 5, wherein the charging circuit includes a trigger switch, the trigger switch being coupled to a charging current source.

7. A reduced switch-on slew low-dropout (LDO) regulator, further comprising:

a pass gate, configured to controllably couple a voltage rail to a regulator output, the control being based in part on a pass gate control signal;

a controllable slew differential amplifier, switchable between a slew-limiting state and a full-slew state, the controllable slew differential amplifier being configured to receive a feedback from the regulator output, and to generate the pass gate control signal, based on a reference voltage and the feedback, at a full-slew rate in the full-slew state, and at a reduced slew rate in the slew-limiting state;

a pass gate disabling circuit, configured to selectively over-ride the pass gate control signal and switch the pass gate OFF;

a pass gate control line, the pass gate control line being configured to carry the pass gate control signal to a control gate of the pass gate, the pass gate disabling circuit comprising a two-position switch, the two-position switch having a disabling position and an operational position;

a feedback element, coupled to the regulator output and to an input of the controllable slew differential amplifier, in a configuration to provide said feedback; and

a compensation network, configured to couple the pass gate control line to the feedback element, the compensation network having a compensation capacitor and a compensation resistor,

the pass gate disabling circuit being further configured to charge the compensation capacitor when the two-position switch is in the disabling position, and to allow the compensation capacitor to discharge the pass gate control line, to a voltage at which the pass gate is operational, in response to switching the two-position switch from the disabling position to the operational position, and

the disabling position providing a short of the control gate to a voltage disabling the pass gate, and the operational position not providing the short of the control gate, the two-position switch being configured to switch between the disabling position and the operational position based on an ON-OFF state of ST_OFF/ON.

8. The reduced switch-on slew LDO regulator of claim 7, wherein a rate of the reduced slew rate is based, at least in part, on at least one of a capacitance of the compensation capacitor or a resistance of the compensation resistor, or both.

9. The reduced switch-on slew LDO regulator of claim 8, wherein the controllable slew differential amplifier includes a switchable tail current source, the switchable tail current source being configured as switchable between sourcing a slew-limiting bias current and a full-slew bias current,

the controllable slew differential amplifier being configured to generate the pass gate control signal at the full-slew rate with the full-slew bias current, and at the reduced slew rate with the slew-limiting bias current, and

the rate of the reduced slew rate being further based, at least in part, on the slew-limiting bias current and at least one of the capacitance of the compensation capacitor or the resistance of the compensation resistor, or both.

10. The reduced switch-on slew LDO regulator of claim 9, further comprising a tail current control circuit, the tail current control circuit being configured to switch the switchable tail current source to the slew-limiting bias current in response to an ON-to-OFF transition of a system ON-OFF signal (ST_ON/OFF) and, at a delay DLY after an OFF-to-ON transition of ST_ON/OFF, to switch the switchable tail current source from the slew-limiting bias current to the full-slew bias current.

11. The reduced switch-on slew LDO regulator of claim 10, the controllable slew differential amplifier being configured to slew, in response to the OFF-to-ON transition of ST_ON/OFF, from an initial zero voltage to approximately Vref, at a slew rate slewing from the initial zero voltage to approximately Vref in a time duration approximately equal to DLY.

12. The reduced switch-on slew LDO regulator of claim 11, wherein the tail current control circuit includes a capacitor and a charging current source, the charging current source being configured to charge the capacitor from a zero voltage to a tail current source mode switch threshold in a charging time duration approximately equal to DLY.

13. A method for reduced switch-on slew low dropout (LDO) regulating with a pass gate controlled by a differential amplifier having differential inputs, and a transistor controlled by one of the differential inputs, comprising:

biasing the transistor with a full-slew bias current;

providing to the differential inputs a reference voltage and a feedback, the feedback being of an output of the pass gate;

in response to an ON-to-OFF transition of a system on/off signal (ST_ON/OFF), disabling the feedback and switching to biasing the transistor with a slew-limiting bias current, the slew-limiting bias current being lower than the full-slew bias current;

in response to an OFF-to-ON transition of ST_ON/OFF, enabling the feedback; and

at a time delayed from the OFF-to-ON transition of ST_ON/OFF by a reduced slew duration, switching to biasing the transistor with the full-slew bias current.

14. The method of claim 13, wherein the switching to biasing the transistor with the full-slew bias current includes commencing, in response to the OFF-to-ON transition of ST_ON/OFF, a charging of a delay capacitor and, in response to a voltage of the delay capacitor reaching a given threshold voltage level, performing the switching to biasing the transistor with the full-slew bias current.

15. The method of claim 13, wherein biasing the transistor with the full-slew bias current comprises:

generating, in response to the ON state of ST_ON/OFF, a biasing current source control signal at an ON level, and

controlling a current source coupled to the transistor based on the biasing current source control signal at the ON level.

16. The method of claim 15, wherein switching to biasing the transistor with the slew-limiting bias current comprises:

generating, in response to the ON-to-OFF transition of ST_ON/OFF, the biasing current source control signal at an OFF level; and

controlling the current source coupled to the transistor based on the biasing current source control signal at the ON level.

17. The method of claim 16, wherein the switching to biasing the transistor with the full-slew bias current includes commencing, in response to the OFF-to-ON transition of ST_ON/OFF, a charging of a delay capacitor and, in response to a voltage of the delay capacitor reaching a given voltage level, performing the switching to biasing the transistor with the full-slew bias current.

18. A reduced switch-on slew low dropout (LDO) regulator comprising:

a differential amplifier, the differential amplifier having difference inputs, an output, and a transistor, the transistor having a gate coupled to one of the difference inputs;

a pass gate, configured as being controlled by the output of the differential amplifier, the pass gate having a pass gate input and a pass gate output, the pass gate input being configured to couple to a power rail, and;

means for receiving a system ON/OFF signal (ST_ON/OFF) and,

in response to an OFF-to-ON transition of ST_ON/OFF, establishing a feedback, the feedback being from the pass gate output to one of the difference inputs, and biasing the transistor with a full-slew bias current, and

in response to an ON-to-OFF transition of ST_ON/OFF, disabling the feedback and switching to biasing of the transistor with a slew-limiting bias current.