Statically speculative compilation and execution

• US 9,235,393 B2
• Filed: 02/27/2014
• Issued: 01/12/2016
• Est. Priority Date: 07/09/2002
• Status: Expired due to Fees

• Current Assignee: III Holdings 2, LLC (Intellectual Ventures LLC), MORITZ, CSABA ANDRAS
• Original Assignee: III Holdings 2, LLC (Intellectual Ventures LLC)
• Inventors: Moritz, Csaba Andras
• Primary Examiner(s): Nahar, Qamrun
• Application Number:
  US14/192,438
• Publication Number:
  US 20140331030A1
• Time in Patent Office: 684 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 8/44 Encoding
• CPC Class Codes: G06F 8/4432 Reducing the energy consumption
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system, for use with a compiler architecture framework, includes performing a statically speculative compilation process to extract and use speculative static information, encoding the speculative static information in an instruction set architecture of a processor, and executing a compiled computer program using the speculative static information, wherein executing supports static speculation driven mechanisms and controls.

Claims

1. A method, for use with a compiler architecture framework, the method comprising:

performing a statically speculative compilation process on a computer program to extract speculative static information; and

encoding the speculative static information in an instruction set architecture of a processor in order to affect power consumption of a processor resource during use thereof, the speculatively static information identifying an access path of the processor resource, the identified path to be utilized at run time to reduce power consumption of an individual use of the processor resource.

2. The method of claim 1, further comprising controlling the processor resource using the speculative static information encoded in the instruction set architecture.

3. The method of claim 1, further comprising operating processor-related mechanisms using the speculative static information encoded in the instruction set architecture.

4. The method of claim 1, wherein the speculative static information comprises at least one of information about processor resource demands or information that contributes to determining processor resource demands.

5. The method of claim 1, wherein the instruction set architecture comprises modified or additional instructions configured to propagate information through code and to store information.

6. The method of claim 1, wherein the statically speculative compilation process exposes speculative static information to run time layers;

and

wherein a microarchitecture to perform execution at run time provides a mechanism to recover from static misprediction.

7. The method of claim 1, wherein the speculative static information comprises a single command encoded in the instruction set architecture, the single command for implementing plural techniques to reduce processor power consumption.

8. The method of claim 7, wherein the statically speculative compilation process determines processor performance and energy tradeoffs during compile-time.

9. The method of claim 1, wherein the speculative static information comprises predictable static information and additional static information that is speculated based on the predictable static information.

10. The method of claim 1, wherein the statically speculative compilation process performs static speculation, the static speculation determining information about execution of the compiled computer program, the static speculation being controlled on application-specific and adaptive bases and being managed with compile-time flags.

11. The method of claim 1, wherein more information about processor resource usage is exposed with speculative static compilation than with predictable static information.

12. A method, comprising:

accessing speculative static information encoded in an instruction set architecture of a processor in order to affect power consumption of a processor resource during use thereof, the speculative static information generated prior to run time, the speculative static information identifying an access path of the processor resource; and

executing a compiled computer program in the processor using the speculative static information encoded in the instruction set architecture, wherein the executing comprises using the access path at run time to reduce resource power consumption for an individual use of the processor resource.

13. The method of claim 12, wherein the executing is performed by microarchitecture that contains an extension, the extension supporting correctness of execution for performing the statically speculative compilation process.

14. The method of claim 13, wherein the extension is comprised of at least one of hardware or software.

15. An apparatus, comprising:

a tagless cache system that is accessible at run time based on speculative static information about a computer program, the speculative static information extracted from the computer program prior to runtime; and

a microarchitecture to access the tagless cache system at run time, the microarchitecture configured to utilize the speculative static information to predict access paths for cache accesses at run time, wherein individual cache accesses predicted using the speculative static information contribute to reduction in cache power and processing device energy consumption.

16. The apparatus of claim 15, wherein the speculative static information is used to register promote cache pointer information to predict cache accesses.

17. The apparatus of claim 15, wherein the speculative static information is used to select cache pointers at run time to predict cache accesses.

18. The apparatus of claim 15, further comprising a scratchpad-memory based cache mechanism;

wherein frequently used data with a low memory footprint is mapped to the scratchpad-memory based cache mechanism.

19. The apparatus of claim 18, wherein associativity and block size in the tagless cache system are logical and programmable.

20. The apparatus of claim 18, further comprising a Cache TLB (Translation Look-ahead Buffer) for capturing statically mispredicted cache pointers and other types of cache pointers.

21. The apparatus of claim 15, wherein individual cache accesses predicted using the speculative static information contribute to reduction in cache power and processor energy consumption.

22. An apparatus, comprising:

means for recovering speculative static information encoded in an instruction set architecture of a processor in order to affect power consumption of a processor resource during use thereof, the speculative static information generated prior to run time, the speculative static information identifying an access path of the processor resource; and

means for utilizing the identified path at run time to reduce power consumption of an individual use of the processor resource at a time of execution of a compiled computer program corresponding to the speculative static information encoded in the instruction set architecture.