Graphical development and deployment of parallel floating-point math functionality on a system with heterogeneous hardware components
First Claim
1. A non-transitory computer accessible memory medium that stores program instructions for configuring a system of heterogeneous hardware components, wherein the program instructions are executable by a processor to:
- create a graphical program that includes floating point math functionality, wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program, wherein the graphical program is targeted for distributed deployment on a system comprising heterogeneous hardware components, including at least one programmable hardware element, at least one digital signal processor (DSP) core, and at least one programmable communication element (PCE);
automatically determine respective portions of the graphical program for deployment to respective ones of the heterogeneous hardware components, including automatically determining respective execution timing for the respective portions;
automatically generate first program code implementing communication functionality between the at least one programmable hardware element and the at least one DSP core, wherein the first program code is targeted for deployment to the at least one programmable communication element; and
automatically generate at least one hardware configuration program from the graphical program and the first program code, wherein said automatically generating comprises compiling the respective portions of the graphical program and the first program code for deployment to respective ones of the heterogeneous hardware components;
wherein the hardware configuration program is deployable to the system, wherein after deployment, the system is configured to execute the graphical program concurrently, including the floating point math functionality.
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Accused Products
Abstract
System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.
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Citations
20 Claims
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1. A non-transitory computer accessible memory medium that stores program instructions for configuring a system of heterogeneous hardware components, wherein the program instructions are executable by a processor to:
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create a graphical program that includes floating point math functionality, wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program, wherein the graphical program is targeted for distributed deployment on a system comprising heterogeneous hardware components, including at least one programmable hardware element, at least one digital signal processor (DSP) core, and at least one programmable communication element (PCE); automatically determine respective portions of the graphical program for deployment to respective ones of the heterogeneous hardware components, including automatically determining respective execution timing for the respective portions; automatically generate first program code implementing communication functionality between the at least one programmable hardware element and the at least one DSP core, wherein the first program code is targeted for deployment to the at least one programmable communication element; and automatically generate at least one hardware configuration program from the graphical program and the first program code, wherein said automatically generating comprises compiling the respective portions of the graphical program and the first program code for deployment to respective ones of the heterogeneous hardware components; wherein the hardware configuration program is deployable to the system, wherein after deployment, the system is configured to execute the graphical program concurrently, including the floating point math functionality. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for configuring a system of heterogeneous hardware components, the method comprising:
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creating a graphical program that includes floating point math functionality, wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program, wherein the graphical program is targeted for distributed deployment on a system comprising heterogeneous hardware components, including at least one programmable hardware element, at least one digital signal processor (DSP) core, and at least one programmable communication element (PCE); automatically determining respective portions of the graphical program for deployment to respective ones of the heterogeneous hardware components, including automatically determining respective execution timing for the respective portions; automatically generating first program code implementing communication functionality between the at least one programmable hardware element and the at least one DSP core, wherein the first program code is targeted for deployment to the at least one programmable communication element; and automatically generating at least one hardware configuration program from the graphical program and the first program code, wherein said automatically generating comprises compiling the respective portions of the graphical program and the first program code for deployment to respective ones of the heterogeneous hardware components; wherein the hardware configuration program is deployable to the system, wherein after deployment, the system is configured to execute the graphical program concurrently, including the floating point math functionality. - View Dependent Claims (15, 16)
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17. A non-transitory computer accessible memory medium that stores program instructions for configuring a system of heterogeneous hardware components, wherein the program instructions are executable by a processor to:
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create a graphical program that includes floating point functionality, wherein the graphical program is targeted for distributed deployment on a system comprising heterogeneous hardware components, including; at least one programmable hardware element; at least one digital signal processor (DSP) core; at least one programmable communication element (PCE); automatically determining respective portions of the graphical program for respective deployment to the heterogeneous hardware components, including automatically determining respective execution timing for the respective portions, wherein the respective portions comprise; a first portion targeted for deployment to the at least one programmable hardware element; and a second portion targeted for deployment to the at least one DSP core; automatically generating program code implementing communication functionality between the at least one programmable hardware element and the at least one DSP core, using the at least one communication element; automatically generating at least one hardware configuration program from the graphical program, including; compiling the first portion of the graphical program for deployment to the at least one programmable hardware element, thereby generating a first portion of the at least one hardware configuration program; compiling the second portion of the graphical program for deployment to the at least one DSP core, thereby generating a second portion of the at least one hardware configuration program; compiling the automatically generated program code implementing communication functionality for deployment to the at least one communication element, thereby generating a third portion of the at least one hardware configuration program; wherein the hardware configuration program is deployable to the system, including; configuring the at least one programmable hardware element with the first portion of the at least one hardware configuration program; configuring the at least one DSP core with the second portion of the at least one hardware configuration program; and configuring the at least one communication element with the third portion of the at least one hardware configuration program; wherein after deployment, the system is configured to execute the graphical program concurrently, including the floating point functionality, wherein during execution; the at least one programmable hardware element performs the functionality of the first portion of the graphical program; the at least one DSP core performs the functionality of the second portion of the graphical program; and the at least one communication element implements communication between the at least one programmable hardware element and the at least one DSP core. - View Dependent Claims (18, 19, 20)
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Specification