Systems and methods for inter-cell interference mitigation in a flash memory
First Claim
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1. A data processing system, the data processing system comprising:
- a soft information correction circuit operable to;
receive soft information corresponding to a series of voltage levels accessed from a block of memory cells;
calculate an offset reduced output of the received soft information by adding an offset value to the received soft information, the offset value being based on an estimated mean value and an estimated variance value associated with the soft information; and
calculate corrected soft information by scaling the offset reduced output based on a scaling value derived from the estimated mean value.
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Abstract
The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods include receiving soft information corresponding to a series of voltage levels accessed from a block of flash memory cells, calculating corrected soft information based upon the received soft information and a variance of the soft information, and applying a data decoding algorithm to the corrected soft information to yield a data output.
25 Citations
20 Claims
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1. A data processing system, the data processing system comprising:
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a soft information correction circuit operable to; receive soft information corresponding to a series of voltage levels accessed from a block of memory cells; calculate an offset reduced output of the received soft information by adding an offset value to the received soft information, the offset value being based on an estimated mean value and an estimated variance value associated with the soft information; and calculate corrected soft information by scaling the offset reduced output based on a scaling value derived from the estimated mean value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for accessing information from a storage device, the method comprising:
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receiving, via a processor, soft information corresponding to a series of voltage levels accessed from a block of flash memory cells; calculating, via the processor, an offset reduced output of the received soft information by adding an offset value to the received soft information, the offset value being based on an estimated mean value and an estimated variance value associated with the soft information; calculating, via the processor, corrected soft information by scaling the offset reduced output based on a scaling value derived from the estimated mean value; and applying, via the processor, a data decoding algorithm to the corrected soft information to yield a data output. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A storage device, the storage device comprising:
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a block of memory cells, wherein each of the memory cells is operable to store a voltage level representing two or more bits; a soft information correction circuit operable to; receive soft information corresponding to a series of voltage levels accessed from the memory cells; calculate an offset reduced output of the received soft information by adding an offset value to the received soft information, the offset value being based on an estimated mean value and an estimated variance value associated with the soft information; calculate corrected soft information by scaling the offset reduced output based on a scaling value derived from the estimated mean value; and a data decoder circuit operable to apply a data decoding algorithm to the corrected soft information to yield a data output.
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Specification