Methods and systems for marking data in a flash-based cache as invalid

• US 9,235,506 B2
• Filed: 08/29/2014
• Issued: 01/12/2016
• Est. Priority Date: 07/14/2010
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Nimble Storage (Hewlett-Packard Enterprise Company)
• Inventors: Maheshwari, Umesh, Mehta, Varun
• Primary Examiner(s): MACKALL, LARRY T
• Application Number:
  US14/473,992
• Publication Number:
  US 20140372686A1
• Time in Patent Office: 501 Days
• Field of Search: 711/113, 711/138
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/28 Using a specific disk cache architecture
• CPC Class Codes: G06F 2212/466 Metadata, control data
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/604 Details relating to cache allocation
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache, and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction.

Claims

1. A method for a storage device having a flash-based cache, a non-volatile random access memory (NVRAM) and a disk-based storage unit, the method comprising:

storing, by a controller of the storage device, a first version of data at an address in the flash-based cache;

storing, by the controller, a second version of the data in the disk-based storage unit but not in the flash-based cache, the second version of the data being different than the first version of the data; and

in response to storing the second version of the data in the disk-based storage unit but not in the flash-based cache, storing, by the controller, only the address of the first version of the data in an invalidate buffer instantiated on the NVRAM so as to mark the first version of the data in the flash-based cache as invalid.

2. The method of claim 1, further comprising, in response to a failure of the invalidate buffer, purging all data from the flash-based cache so as to prevent the controller from serving stale data from the flash-based cache.

3. The method of claim 1, further comprising, in response to the controller being unable to store further addresses in the invalidate buffer, invalidating data in the flash-based cache that has been marked as invalid in the NVRAM.

4. The method of claim 1, wherein a maximum amount of information that can be stored in the NVRAM is less than a maximum amount of information that can be stored in the flash-based cache.

5. A storage device, comprising a flash-based cache, a disk-based storage unit, a non-volatile random access memory (NVRAM) and a controller, the controller (i) communicatively coupled to the flash-based cache, the disk-based storage unit and the NVRAM;

and (ii) configured to;

store a first version of data at an address in the flash-based cache;

store a second version of the data in the disk-based storage unit but not in the flash-based cache, the second version of the data being different than the first version of the data; and

in response to storing the second version of the data in the disk-based storage unit but not in the flash-based cache, store only the address of the first version of the data in an invalidate buffer instantiated on the NVRAM so as to mark the first version of the data in the flash-based cache as invalid.

6. The storage device of claim 5, wherein the controller is further configured to, in response to a failure of the invalidate buffer, purge all data from the flash-based cache so as to prevent the controller from serving stale data from the flash-based cache.

7. The storage device of claim 5, wherein the controller is further configured to, in response to the controller being unable to store further addresses in the invalidate buffer, invalidate data in the flash-based cache that has been marked as invalid in the NVRAM.

8. The storage device of claim 5, wherein a maximum amount of information that can be stored in the NVRAM is less than a maximum amount of information that can be stored in the flash-based cache.

9. A non-transitory computer-readable storage medium comprising software instructions that, when executed by a controller of a storage device, cause the controller to:

store a first version of data at an address in a flash-based cache of the storage device;

store a second version of the data in a disk-based storage unit of the storage device but not in the flash-based cache, the second version of the data being different than the first version of the data; and

in response to storing the second version of the data in the disk-based storage unit but not in the flash-based cache, store only the address of the first version of the data in an invalidate buffer instantiated on a non-volatile random access memory (NVRAM) of the storage device so as to mark the first version of the data in the flash-based cache as invalid.

10. The non-transitory computer-readable storage medium of claim 9, further comprising software instructions that, when executed by the controller, cause the controller to, in response to a failure of the invalidate buffer, purge all data from the flash-based cache so as to prevent the controller from serving stale data from the flash-based cache.

11. The non-transitory computer-readable storage medium of claim 9, further comprising software instructions that, when executed by the controller, cause the controller to, in response to the controller being unable to store further addresses in the invalidate buffer, invalidate data in the flash-based cache that has been marked as invalid in the NVRAM.

12. The non-transitory computer-readable storage medium of claim 9, wherein a maximum amount of information that can be stored in the NVRAM is less than a maximum amount of information that can be stored in the flash-based cache.