Voltage kick to non-selected word line during programming

• US 9,236,128 B1
• Filed: 02/02/2015
• Issued: 01/12/2016
• Est. Priority Date: 02/02/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Mui, Man, Louie, Kenneth, Nguyen, Khanh
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/612,010
• Time in Patent Office: 344 Days
• Field of Search: 365/185.11, 365/185.05, 365/185.23, 365/185.17, 365/230.03, 365/230.06
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

When applying a programming voltage at one end of a word line of a non-volatile memory circuit, if the word line has a large RC constant the far end of the word line will not rise as fast as the driven end, which can adversely affect device performance. To more quickly raise the voltage on the selected word line, a voltage kick is applied to non-selected word lines, such as dummy word lines, by way of a non-selected sub-block of the selected block. The channel of NAND strings in the non-selected sub-block is used to transfer the kick to the far end of the selected word line of the selected sub-block.

Claims

1. A non-volatile memory circuit, comprising:

an array having a plurality of blocks formed according to a NAND type of architecture of a plurality of non-volatile memory cells formed along word lines and connected in series between select gates, each of the blocks having a plurality of sub-blocks, where individual word line portions of the sub-blocks of the same word line of the same block are commonly connected and the select gates of control gates of sub-blocks are connected independently of the select gates of other sub-blocks of the same block;

driver circuitry connectable to the word lines and the select gates to provide programming voltage levels thereto, wherein the driver circuitry is connectable at a first, but not a second, end of each of the word lines, and wherein at the second end thereof each of the individual word line portions of sub-blocks of the same word line of a block are commonly connected;

decoding circuitry by which the driver circuitry is connectable to the word lines and the select gates; and

on-chip control circuitry connected to the driver circuit and decoder circuitry, whereby when performing a programming operation for memory cells on a selected word line for a selected sub-block of a selected block;

an initial block biasing operation of the selected block is performed in which select gates of non-selected sub-blocks of the selected block are biased to be off and non-selected word lines of the selected block are biased to one of one or more pass voltages, except for a first set of one or more non-selected word lines that are set to a first voltage level, wherein the pass voltages are sufficient to allow a memory cell to conduct independently of a data state written thereto and wherein the first voltage will allow a memory cell to conduct for some but not all data states programmable thereto; and

, with the selected block biased according to the initial block biasing operation, applying a programming pulse to the selected word line and, while applying the programming pulse, raising the voltage level on one or more of the first set of word lines from the first voltage to a pass voltage.

2. The non-volatile memory circuit of claim 1, wherein the array includes word lines storing user data and one or more dummy word lines not used for the storing of user data, the memory cells of the dummy word lines formed between the memory cells of word lines storing user data and a select gate, wherein the first set of non-selected word lines includes one or more dummy word lines.

3. The non-volatile memory circuit of claim 2, wherein the first set of non-selected word lines includes a source-side dummy word lines.

4. The non-volatile memory circuit of claim 2, wherein the first set of non-selected word lines includes a drain-side dummy word lines.

5. The non-volatile memory circuit of claim 1, wherein the memory circuit is a monolithic three-dimensional semiconductor memory device having the memory cells arranged in multiple physical levels above a silicon substrate and comprising a charge storage medium, wherein NAND strings run in a vertical direction relative to the substrate, and wherein the word lines run in a horizontal direction relative to the substrate.

6. A method of performing a programming operation for memory cells on a selected word line for a selected sub-block of a selected block of a non-volatile memory circuit, the memory circuit having an array having of a plurality of blocks formed according to a NAND type of architecture of a plurality of non-volatile memory cells formed along word lines and connected in series between select gates, each of the blocks having a plurality of sub-blocks, where individual word line portions of the sub-blocks of the same word line of the same block are commonly connected and the select gates of control gates of sub-blocks are connected independently of the select gates of other sub-blocks of the same block, and having driver circuitry connectable to the word lines and the select gates to provide programming voltage levels thereto, wherein the driver circuitry is connectable at a first, but not a second, end of each of the word lines, and wherein at the second end thereof each of the individual word line portions of sub-blocks of the same word line of a block are commonly connected, the method comprising:

performing an initial block biasing operation of the selected block, comprising;

biasing select gates of non-selected sub-blocks of the selected block to be off; and

driving from the first end thereof non-selected word lines of the selected block, where the non-selected word lines of the selected block are biased to one of one or more pass voltages, except for a first set of one or more non-selected word lines that are set to a first voltage level, wherein the pass voltages are sufficient to allow a memory cell to conduct independently of a data state written thereto and wherein the first voltage will allow a memory cell to conduct for some but not all data states programmable thereto; and

,

with the selected block biased according to the initial block biasing operation, applying a programming pulse to the selected word line from the first end thereof; and

while applying the programming pulse, raising the voltage level on one or more of the first set of word lines from the first voltage to a pass voltage.

7. The method of claim 6, wherein the array includes word lines storing user data and one or more dummy word lines not used for the storing of user data, the memory cells of the dummy word lines formed between the memory cells of word lines storing user data and a select gate, wherein the first set of non-selected word lines includes one or more dummy word lines.

8. The method of claim 7, wherein the first set of non-selected word lines includes a source-side dummy word lines.

9. The method of claim 7, wherein the first set of non-selected word lines includes a drain-side dummy word lines.

10. The method of claim 6, wherein the memory circuit is a monolithic three-dimensional semiconductor memory device having the memory cells arranged in multiple physical levels above a silicon substrate and comprising a charge storage medium, wherein NAND strings run in a vertical direction relative to the substrate, and wherein the word lines run in a horizontal direction relative to the substrate.

11. A non-volatile memory circuit, comprising:

an array having a plurality of blocks formed according to a NAND type of architecture of a plurality of non-volatile memory cells formed along word lines and connected in series between select gates, each of the blocks having a plurality of sub-blocks, where individual word line portions of the sub-blocks of the same word line of the same block are commonly connected and the select gates of control gates of sub-blocks are connected independently of the select gates of other sub-blocks of the same block, wherein the memory circuit is a monolithic three-dimensional semiconductor memory device having the memory cells arranged in multiple physical levels above a silicon substrate and comprising a charge storage medium, wherein NAND strings run in a vertical direction relative to the substrate, and wherein the word lines run in a horizontal direction relative to the substrate;

driver circuitry connectable to the word lines and the select gates to provide programming voltage levels thereto, wherein the driver circuitry is connectable at a first, but not a second, end of each of the word lines, and wherein at the second end thereof each of the individual word line portions of sub-blocks of the same word line of a block are commonly connected;

decoding circuitry by which the driver circuitry is connectable to the word lines and the select gates; and

on-chip control circuitry connected to the driver circuit and decoder circuitry, whereby when performing a programming operation for memory cells on a selected word line for a selected sub-block of a selected block;

an initial block biasing operation of the selected block is performed in which select gates of non-selected sub-blocks of the selected block are biased to be off and non-selected word lines of the selected block are biased to one of one or more pass voltages, except for a first set of one or more non-selected word lines that are set to a first voltage level, wherein the pass voltages are sufficient to allow a memory cell to conduct independently of a data state written thereto and wherein the first voltage will allow a memory cell to conduct for some but not all data states programmable thereto; and

, with the selected block biased according to the initial block biasing operation, applying a programming pulse to the selected word line and, while applying the programming pulse, raising the voltage level on one or more of the first set of word lines from the first voltage to a pass voltage.

12. The non-volatile memory circuit of claim 11, wherein the array includes word lines storing user data and one or more dummy word lines not used for the storing of user data, the memory cells of the dummy word lines formed between the memory cells of word lines storing user data and a select gate, wherein the first set of non-selected word lines includes one or more dummy word lines.

13. The non-volatile memory circuit of claim 12, wherein the first set of non-selected word lines includes a source-side dummy word lines.

14. The non-volatile memory circuit of claim 12, wherein the first set of non-selected word lines includes a drain-side dummy word lines.