Flash memory integrated circuit with compression/decompression CODEC

• US 9,236,129 B2
• Filed: 07/17/2009
• Issued: 01/12/2016
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Jun Young
• Primary Examiner(s): Hwa, Shyue Jiunn
• Application Number:
  US12/458,641
• Publication Number:
  US 20100077133A1
• Time in Patent Office: 2,370 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory.

Claims

1. A flash memory integrated circuit with a compression codec, comprising:

at least one memory block including a plurality of pages;

a type decision circuit configured to determine whether input data is compressed by comparing a type of the input data with a predetermined compressing type and to provide a logic value corresponding to the determination;

a compression codec circuit configured to compress the input data according to the provided logic value when the input data is uncompressed and not to compress the input data according to the provided logic value when the input data is compressed and to generate identification information indicating that the input data is the compressed input data; and

a controller circuit configured to generate a control signal in order to sequentially write the input data when the controller circuit is configured to receive originally compressed input data from the compression codec circuit and a control signal in order to sequentially write the compressed input data and the identification information when the controller circuit is configured to receive the compressed input data and the identification information from the compression codec circuit in at least one page among the plurality of pages,

wherein the controller circuit is configured to generate the control signal to control voltages to be applied to a word line or a bit line that is connected to the at least one page.

2. The flash memory integrated circuit of claim 1, wherein the input data is multimedia data.

3. The flash memory integrated circuit of claim 1, wherein the at least one memory block is a memory block of a NAND flash memory.

4. A flash memory integrated circuit with a compression codec, comprising:

at least one memory block including a plurality of pages;

a controller circuit configured to generate a control signal in order to read written data that is written in at least one page among the plurality of pages,

wherein the written data is a compressed input data compressed by a compression codec circuit when an input data is an uncompressed input data or originally compressed input data not compressed by the compression codec circuit after by comparing a type of the input data with a predetermined compressing type and is determined by obtaining identification information from the compression codec circuit indicating that the input data is the compressed input data whether the written data is compressed;

a compression codec circuit configured to decompress the read written data determined as the compressed input data by the control signal including identification information from a controller circuit and to not decompress the read written data determined as originally compressed input data by using a control signal including identification information from the controller circuit,

wherein the compressed data is written in the at least one page by the compression codec circuit,

wherein the controller circuit is configured to generate the control signal to control voltages to be applied to a word line or a bit line that is connected to the at least one page.

5. The flash memory integrated circuit of claim 4, wherein:

identification information capable of identifying the compressed data is further stored in the at least one memory block.

6. A method of operating a flash memory with a compression codec, the method comprising:

determining, by a type decision circuit, whether input data is compressed by comparing a type of the input data with a predetermined compressing type,

wherein the type decision circuit provides a logic value corresponding to the determination;

compressing, by the compression codec circuit, the input data of the flash memory; and

generating the control signal in order to write the input data when a controller circuit receives originally compressed input data from the compression codec circuit and the control signal in order to write the compressed input data and the identification information when a controller circuit receives the compressed input data and the identification information from the compression codec circuit in at least one page among a plurality of pages that is included in at least one memory block of the flash memory,

wherein the compression codec circuit is configured to compress the input data according to the provided logic value when the input data is uncompressed, and not compresses the input data according to the provided logic value when the input data is compressed and generate identification information indicating that the input data is the compressed input data,

wherein the controller circuit is configured to generate the control signal to control voltages to be applied to a word line or a bit line that is connected to the at least one page.

7. A non-transitory computer-readable recording medium storing a program for causing a processor to implement the method of claim 6.

8. A method of operating a flash memory with a compression codec, the method comprising:

generating a control signal in order to read written data that is written in at least one page among a plurality of pages included in at least one memory block of the flash memory,

wherein the written data is a compressed input data compressed by the compression codec circuit when an input data is an uncompressed input data or originally compressed input data not compressed by the compression codec circuit after by comparing a type of the input data with a predetermined compressing type and is determined by obtaining identification information from a compression codec circuit indicating that the input data is the compressed input data whether the written data is compressed;

decompressing, by the compression codec circuit, the read written data determined as the compressed input data by using the control signal including identification information from the controller circuit and to not decompress the read written data determined as originally compressed input data by using the control signal including identification information from the controller circuit,

wherein the compressed data is written in the at least one page by the compression codec circuit,

wherein the controller circuit is configured to generate the control signal to control voltages to be applied to a word line or a bit line that is connected to the at least one page.

9. The method of claim 8, wherein:

identification information capable of identifying the compressed data is further stored in the at least one memory block.