Memory management method, memory control circuit unit and memory storage apparatus

• US 9,236,148 B2
• Filed: 04/28/2014
• Issued: 01/12/2016
• Est. Priority Date: 02/14/2014
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Chu, Chien-Hua
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US14/263,979
• Publication Number:
  US 20150234692A1
• Time in Patent Office: 624 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2046 where the redundant components share persistent storage G06F11/2043 takes precedence
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A memory management method, a memory control circuit unit using the method, and a memory storage apparatus using the method are provided. The memory management method includes determining whether a use count of the rewritable non-volatile memory module is greater than a use count threshold; based on a result of the determination, sorting each physical erasing unit in a spare area in an ascending manner according to an erasing count of each physical erasing unit in the spare area or according to the number of maximum bit errors of the physical erasing units in the spare area, so as to form a plurality of sorted physical erasing units; and selecting the foremost physical erasing unit from the spare area to write data according to the sorted physical erasing units. By applying the memory management method, the lifespan of the rewritable non-volatile memory module may be effectively prolonged.

Claims

1. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module having a plurality of physical erasing units, the memory management method comprising:

recording an erasing count of each of the physical erasing units;

grouping the physical erasing units at least into a spare area and a data area;

determining whether a use count of the rewritable non-volatile memory module is greater than a use count threshold;

if the use count of the rewritable non-volatile memory module is not greater than the use count threshold, sorting each of the physical erasing units in the spare area in an ascending manner according to the erasing count of each of the physical erasing units in the spare area to form a plurality of sorted physical erasing units;

if the use count of the rewritable non-volatile memory module is greater than the use count threshold, sorting each of the physical erasing units in the spare area in the ascending manner according to the number of maximum bit errors of the physical erasing units in the spare area to form the sorted physical erasing units; and

selecting a first physical erasing unit from the spare area to write data according to the sorted physical erasing units, wherein the first physical erasing unit is a foremost physical erasing unit of the sorted physical erasing units.

2. The memory management method as recited in claim 1, wherein the step of determining whether the use count of the rewritable non-volatile memory module is greater than the use count threshold comprises:

calculating an average erasing count of the physical erasing units according to the erasing count of each of the physical erasing units;

determining whether the average erasing count of the physical erasing units is greater than a erasing count threshold;

if the average erasing count of the physical erasing units is greater than the erasing count threshold, determining the use count of the rewritable non-volatile memory module is greater than the use count threshold; and

if the average erasing count of the physical erasing units is not greater than the erasing count threshold, determining the use count of the rewritable non-volatile memory module is not greater than the use count threshold.

3. The memory management method as recited in claim 1, wherein the step of determining whether the use count of the rewritable non-volatile memory module is greater than the use count threshold comprises:

determining whether the erasing count of at least one of the physical erasing units is greater than a erasing count threshold;

if the erasing count of the at least one of the physical erasing units is greater than the erasing count threshold, determining the use count of the rewritable non-volatile memory module is greater than the use count threshold; and

if the erasing count of each of the physical erasing units is not greater than the erasing count threshold, determining the use count of the rewritable non-volatile memory module is not greater than the use count threshold.

4. The memory management method as recited in claim 1, wherein each of the physical erasing units comprises a plurality of physical programming units, and each of the physical programming units stores at least one error checking and correcting frame, the memory management method comprising:

continuously recording the number of bit errors in each of the at least one error checking and correcting frame in the first physical erasing unit among the physical erasing units; and

applying the number of maximum bit errors as the number of maximum bit errors of the first physical erasing unit.

5. The memory management method as recited in claim 1, wherein the step of sorting each of the physical erasing units in the spare area in the ascending manner according to the erasing count of each of the physical erasing units in the spare area to form the sorted physical erasing units comprises:

obtaining an erasing count weighted value by multiplying the erasing count of each of the physical erasing units in the spare area by a third predetermined value; and

sorting each of the physical erasing units in the spare area in the ascending manner according to the erasing count weighted value to form the sorted physical erasing units.

6. The memory management method as recited in claim 1, wherein the step of sorting each of the physical erasing units in the spare area in the ascending manner according to the number of maximum bit errors of the physical erasing units in the spare area to form the sorted physical erasing units comprises:

calculating a weighted value corresponding to each of the physical erasing units according to the erasing count and the number of maximum bit errors of each of the physical erasing units in the spare area and sorting the physical erasing units in the spare area in the ascending manner according to the weighted value to form the sorted physical erasing units.

7. The memory management method as recited in claim 6, wherein the step of calculating the weighted value corresponding to each of the physical erasing units according to the erasing count and the number of maximum bit errors of each of the physical erasing units in the spare area comprises:

generating an erasing count weighted value corresponding to each of the physical erasing units by multiplying the erasing count of each of the physical erasing units by a first predetermined value;

generating a weighted value of the number of maximum bit errors corresponding to each of the physical erasing units by multiplying the number of maximum bit errors of each of the physical erasing units by a second predetermined value; and

adding each of the erasing count weighted values and each of the weighted values of the number of maximum bit errors and applying the added values as the weighted value corresponding to each of the physical erasing units.

8. A memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit comprising:

a host interface configured to be coupled to a host system; and

a memory interface configured to be coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units; and

a memory management circuit coupled to the host interface and the memory interface and configured to record an erasing count of each of the physical erasing units,

wherein the memory management circuit is further configured to group the physical erasing units at least into a spare area and a data area,

wherein the memory management circuit is further configured to determine whether a use count of the rewritable non-volatile memory module is greater than a use count threshold,

if the use count of the rewritable non-volatile memory module is not greater than the use count threshold, the memory management circuit is further configured to sort each of the physical erasing units in the spare area in an ascending manner according to the erasing count of each of the physical erasing units in the spare area to form a plurality of sorted physical erasing units,

and if the use count of the rewritable non-volatile memory module is greater than the use count threshold, the memory management circuit is further configured to sort each of the physical erasing units in the spare area in the ascending manner according to the number of maximum bit errors of the physical erasing units in the spare area to form the sorted physical erasing units,

wherein the memory management circuit is further configured to issue a command sequence to the rewritable non-volatile memory module, the command sequence indicates selecting a first physical erasing unit from the spare area to write data according to the sorted physical erasing units, and the first physical erasing unit is a foremost physical erasing unit of the sorted physical erasing units.

9. The memory control circuit unit as recited in claim 8, wherein in the operation of determining whether the use count of the rewritable non-volatile memory module is greater than the use count threshold, the memory management circuit calculates an average erasing count of the physical erasing units according to the erasing count of each of the physical erasing units and determines whether the average erasing count of the physical erasing units is

greater than a erasing count threshold,

if the average erasing count of the physical erasing units is greater than the erasing count threshold, the memory management circuit determines the use count of the rewritable non-volatile memory module is greater than the use count threshold,

and if the average erasing count of the physical erasing units is not greater than the erasing count threshold, the memory management circuit determines the use count of the rewritable non-volatile memory module is not greater than the use count threshold.

10. The memory control circuit unit as recited in claim 8, wherein in the operation of determining whether the use count of the rewritable non-volatile memory module is greater than the use count threshold, the memory management circuit determines whether the erasing count of at least one of the physical erasing units is greater than a erasing count threshold,

if the erasing count of the at least one of the physical erasing units is greater than the erasing count threshold, the memory management circuit determines the use count of the rewritable non-volatile memory module is greater than the use count threshold,

and if the erasing count of each of the physical erasing units is not greater than the erasing count threshold, the memory management circuit determines the use count of the rewritable non-volatile memory module is not greater than the use count threshold.

11. The memory control circuit unit as recited in claim 8, wherein each of the physical erasing units comprises a plurality of physical programming units, and each of the physical programming units stores at least one error checking and correcting frame, wherein the memory management circuit is further configured to continuously record the number of bit errors in each of the at least one error checking and correcting frame in the first physical erasing unit and apply the number of maximum bit errors as the number of maximum bit errors of the first physical erasing unit.

12. The memory control circuit unit as recited in claim 8, in the operation of sorting each of the physical erasing units in the spare area in the ascending manner according to the erasing count of each of the physical erasing units in the spare area to form the sorted physical erasing units,

the memory management circuit obtains an erasing count weighted value by multiplying the erasing count of each of the physical erasing units in the spare area by a third predetermined value, and

the memory management circuit sorts each of the physical erasing units in the spare area in the ascending manner according to the erasing count weighted value to form the sorted physical erasing units.

13. The memory control circuit unit as recited in claim 8,

wherein in the operation of sorting each of the physical erasing units in the spare area in the ascending manner according to the number of maximum bit errors of the physical erasing units in the spare area to form the sorted physical erasing units, the memory management circuit calculates a weighted value corresponding to each of the physical erasing units according to the erasing count and the number of maximum bit errors of each of the physical erasing units in the spare area and sorts the physical erasing units in the spare area in the ascending manner according to the weighted value to form the sorted physical erasing units.

14. The memory control circuit unit as recited in claim 13, wherein in the operation of calculating the weighted value corresponding to each of the physical erasing units according to the erasing count and the number of maximum bit errors of each of the physical erasing units in the spare area, the memory management circuit generates an erasing count weighted value corresponding to each of the physical erasing units by multiplying the erasing count of each of the physical erasing units by a first predetermined value, generates a weighted value of the number of maximum bit errors corresponding to each of the physical erasing units by multiplying the number of maximum bit errors of each of the physical erasing units by a second predetermined value, and adds each of the erasing count weighted values and each of the weighted values of the number of maximum bit errors and applies the added values as the weighted value corresponding to each of the physical erasing units.

15. A memory storage apparatus comprising:

a connection interface unit configured to be coupled to a host system;

a rewritable non-volatile memory module having a plurality of physical erasing units; and

a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module and configured to record an erasing count of each of the physical erasing units,

wherein the memory control circuit unit is further configured to group the physical erasing units at least into a spare area and a data area,

wherein the memory control circuit unit is further configured to determine whether a use count of the rewritable non-volatile memory module is greater than a use count threshold,

if the use count of the rewritable non-volatile memory module is not greater than the use count threshold, the memory control circuit unit is further configured to sort each of the physical erasing units in the spare area in an ascending manner according to the erasing count of each of the physical erasing units in the spare area to form a plurality of sorted physical erasing units,

and if the use count of the rewritable non-volatile memory module is greater than the use count threshold, the memory control circuit unit is further configured to sort each of the physical erasing units in the spare area in the ascending manner according to the number of maximum bit errors of the physical erasing units in the spare area to form the sorted physical erasing units,

wherein the memory control circuit unit is further configured to select a first physical erasing unit from the spare area to write data according to the sorted physical erasing units, and the first physical erasing unit is a foremost physical erasing unit of the sorted physical erasing units.

16. The memory storage apparatus as recited in claim 15, wherein in the operation of determining whether the use count of the rewritable non-volatile memory module is greater than the use count threshold, the memory control circuit unit calculates an average erasing count of the physical erasing units according to the erasing count of each of the physical erasing units and determines whether the average erasing count of the physical erasing units is greater than a erasing count threshold,

if the average erasing count of the physical erasing units is greater than the erasing count threshold, the memory control circuit unit determines the use count of the rewritable non-volatile memory module is greater than the use count threshold,

if the average erasing count of the physical erasing units is not greater than the erasing count threshold, the memory control circuit unit determines the use count of the rewritable non-volatile memory module is not greater than the use count threshold.

17. The memory storage apparatus as recited in claim 15, in the operation of determining whether the use count of the rewritable non-volatile memory module is greater than the use count threshold, the memory control circuit unit determines whether the erasing count of at least one of the physical erasing units is greater than a erasing count threshold,

if the erasing count of the at least one of the physical erasing units is greater than the erasing count threshold, the memory control circuit unit determines the use count of the rewritable non-volatile memory module is greater than the use count threshold,

if the erasing count of each of the physical erasing units is not greater than the erasing count threshold, the memory control circuit unit determines the use count of the rewritable non-volatile memory module is not greater than the use count threshold.

18. The memory storage apparatus as recited in claim 15, wherein each of the physical erasing units comprises a plurality of physical programming units, and each of the physical programming units stores at least one error checking and correcting frame, wherein the memory control circuit unit is further configured to continuously record an the number of bit errors in each of the at least one error checking and correcting frame in the first physical erasing unit and apply the number of maximum bit errors as the number of maximum bit errors of the first physical erasing unit.

19. The memory storage apparatus as recited in claim 15, wherein in the operation of sorting each of the physical erasing units in the spare area in the ascending manner according to the erasing count of each of the physical erasing units in the spare area to form the sorted physical erasing units,

the memory control circuit unit obtains an erasing count weighted value by multiplying the erasing count of each of the physical erasing units in the spare area by a third predetermined value, and

the memory control circuit unit sorts each of the physical erasing units in the spare area in the ascending manner according to the erasing count weighted value to form the sorted physical erasing units.

20. The memory storage apparatus as recited in claim 15,

wherein in the operation of sorting each of the physical erasing units in the spare area in the ascending manner according to the number of maximum bit errors of the physical erasing units in the spare area to form the sorted physical erasing units, the memory control circuit unit calculates a weighted value corresponding to each of the physical erasing units according to the erasing count and the number of maximum bit errors of each of the physical erasing units in the spare area and sorts the physical erasing units in the spare area in the ascending manner according to the weighted value to form the sorted physical erasing units.

21. The memory storage apparatus as recited in claim 20, wherein in the operation of calculating the weighted value corresponding to each of the physical erasing units according to the erasing count and the number of maximum bit errors of each of the physical erasing units in the spare area, the memory control circuit unit generates an erasing count weighted value corresponding to each of the physical erasing units by multiplying the erasing count of each of the physical erasing units by a first predetermined value, generates a weighted value of the number of maximum bit errors corresponding to each of the physical erasing units by multiplying the number of maximum bit errors of each of the physical erasing units by a second predetermined value, and adds each of the erasing count weighted values and each of the weighted values of the number of maximum bit errors and applies the added values as the weighted value corresponding to each of the physical erasing units.