Contact plugs in SRAM cells and the method of forming the same

• US 9,236,300 B2
• Filed: 11/30/2012
• Issued: 01/12/2016
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon-Jhy
• Primary Examiner(s): Diallo, Mamadou
• Assistant Examiner(s): Chang, Jay C
• Application Number:
  US13/691,367
• Publication Number:
  US 20140151812A1
• Time in Patent Office: 1,138 Days
• Field of Search: 438/717, 438/734, 438/736, 438738-740, 438742-744, 438749-751
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A method includes forming a dielectric layer over a portion of an SRAM cell. The SRAM cell includes a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor, and a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively. A first mask layer is formed over the dielectric layer and patterned. A second mask layer is formed over the dielectric layer and patterned. The dielectric layer is etched using the first mask layer and the second mask layer in combination as an etching mask, wherein a contact opening is formed in the dielectric layer. A contact plug is formed in the contact opening.

Claims

1. A method comprising:

forming a dielectric layer over a portion of a Static Random Access Memory (SRAM) cell, wherein the SRAM cell comprises;

a first pull-up transistor and a second pull-up transistor;

a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor; and

a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively;

forming and patterning a first mask layer over the dielectric layer, wherein the forming and the patterning of the first mask layer includes;

patterning a photo resist material disposed over the first mask layer; and

etching the first mask layer to transfer a pattern from the patterned photo resist material to the first mask layer such that the etched first mask layer includes an opening extending over a first source/drain fin of the SRAM cell, over a second source/drain fin of the SRAM cell, and over a third source/drain fin of the SRAM cell, wherein the opening extends uninterrupted across the entire SRAM cell along one dimension of the SRAM cell and has a substantially uniform width measured perpendicular to the one dimension;

thereafter, forming a second mask layer over the dielectric layer;

etching the dielectric layer using the first mask layer and the second mask layer in combination as an etching mask, wherein a first contact opening and a second contact opening are formed in the dielectric layer from the opening in the etched first mask layer;

wherein the first contact opening extends over and exposes both the first source/drain fin and the third source/drain fin;

forming a first discrete contact plug in the first contact opening electrically connected to the first source/drain fin and the third source/drain fin; and

forming a second discrete contact plug in the second contact opening connected to the second source/drain fin.

2. The method of claim 1, wherein the first mask layer comprises a material selected from the group consisting essentially of a silicon oxide based dielectric, silicon oxynitride, silicon nitride, polysilicon, amorphous silicon, a carbon-containing dielectric material, a nitrogen-containing dielectric material, an organic material, a refractory metal, and combinations thereof.

3. The method of claim 2, wherein the second mask layer comprises a photo resist, and wherein the second mask layer is over the first mask layer.

4. The method of claim 1, wherein after the step of patterning the first mask layer, the first mask layer forms a continuous layer with a first long contact opening therein, wherein the first long contact opening has a longitudinal direction parallel to a long boundary of the SRAM cell, and wherein the first long contact opening has a length greater than or equal to a length of the long boundary.

5. The method of claim 4, wherein the continuous layer further comprises a second long contact opening therein, wherein the second long contact opening has a longitudinal direction parallel to a long boundary of the SRAM cell, and wherein the second long contact opening has a length smaller than the length of the long boundary.

6. The method of claim 5, wherein the second long contact opening extends to a boundary of the SRAM cell.

7. The method of claim 5, wherein the second long contact opening does not extend to any boundary of the SRAM cell.

8. The method of claim 1, wherein after the step of patterning the first mask layer, the first mask layer forms islands that are separated from each other.

9. The method of claim 1, wherein at a time the first discrete contact plug is formed, the second discrete contact plug is formed simultaneous.

10. The method of claim 1, wherein the first discrete contact plug continuously extends over, and interconnects, a drain of the first pull-down transistor and a drain of the first pull-up transistor.

11. A method comprising:

forming a Static Random Access Memory (SRAM) cell comprising a plurality of gate electrodes, and a plurality of active region strips, wherein the plurality of active region strips form transistors with the plurality of gate electrodes;

forming an Inter-Layer Dielectric (ILD) over the plurality of gate electrodes and the plurality of active region strips;

forming a first mask layer over the ILD, wherein the first mask layer covers first portions of the ILD, with second portions of the ILD exposed through openings in the first mask layer, wherein the forming of the first mask layer includes;

forming a resist over the first mask layer;

patterning the resist; and

etching the first mask layer using the patterned resist to form the openings through which the second portions of the ILD are exposed,

wherein the openings include a first opening of the first mask layer disposed over a first active region, a second active region, and a third active region of the plurality of active region strips,

wherein the first opening of the first mask layer extends uninterrupted from a first boundary of the SRAM cell to a second boundary of the SRAM cell opposite the first boundary, and

wherein the first opening has a substantially uniform width measured parallel to the first boundary and the second boundary;

forming a second mask layer, wherein the second mask layer comprises portions filled into parts of the openings in the first mask layer;

etching the ILD using the first mask layer and the second mask layer as an etching mask to form a plurality of contact openings in the ILD, wherein the etching forms a first contact opening and a second contact opening underlying the opening of the first mask layer;

wherein the first contact opening extends over and exposes both the first active region and the third active region; and

forming a plurality of contact plugs in the plurality of contact openings, wherein the plurality of contacts plugs includes;

a first discrete contact plug within the first contact opening and electrically connected to the first active region and the third active region; and

a second discrete contact plug within the second contact opening and electrically connected to the second active region; and

wherein the active regions include source and drain regions of the transistors.

12. The method of claim 11,

wherein the openings in the first mask layer further comprise a second opening overlapping, and having a longitudinal direction parallel to, a third boundary of the SRAM cell, and

wherein the third boundary is perpendicular to the first boundary and the second boundary.

13. The method of claim 12, wherein the second mask layer comprises strips having longitudinal directions perpendicular to the longitudinal direction of the second opening.

14. The method of claim 11, wherein the first mask layer comprises a hard mask material, and the second mask layer comprises a photo resist.

15. The method of claim 11, wherein the step of forming the plurality of contact plugs comprises:

forming the first discrete contact plug over and connected to a drain of a pull-down transistor of the SRAM cell and to a drain of a pull-up transistor of the SRAM cell.

16. A method comprising:

receiving a substrate having a circuit device formed thereupon, wherein the circuit device includes;

a plurality of active regions of a plurality of transistors disposed on the substrate;

a material layer disposed on the substrate;

a first masking layer disposed on the material layer; and

a photoresist disposed on the first masking layer;

patterning the photoresist;

etching the first masking layer to remove a portion of the first masking layer exposed by the patterned photoresist to form a cavity within the first masking layer extending over a first active region, a second active region, and a third active region of the plurality of active regions, wherein the cavity extends uninterrupted from a first cell boundary of the circuit device to an opposing second cell boundary of the circuit device, and wherein the cavity has a substantially uniform width measured parallel to the first cell boundary and the second cell boundary;

forming a second masking layer on the substrate and within the cavity;

patterning the second masking layer;

etching the material layer to remove a portion of the material layer exposed by the etched first masking layer and the patterned second masking layer to form a first contact opening and a second contact opening from the cavity;

wherein the first contact opening extends over and exposes both the first active region and the third active region; and

forming a plurality of contact plugs within and extending through the etched material layer, wherein the plurality of contact plugs includes;

a first discrete plug disposed in the first contact opening and electrically coupled to the first active region and the third active region, and

a second discrete plug disposed in the second contact opening and coupled to the second active region; and

wherein the active regions include source and drain regions of the transistors.

17. The method of claim 16, wherein the circuit device includes an SRAM cell over which the material layer is formed, and wherein the first cell boundary and the second cell boundary are boundaries of the SRAM cell.

18. The method of claim 16, wherein the circuit device defines a standard cell, and wherein the first cell boundary and the second cell boundary are boundaries of the standard cell.

19. The method of claim 17, wherein the first active region corresponds to a first cross-coupled invertor of the SRAM cell, and wherein the second active region corresponds to a second cross-coupled invertor of the SRAM cell.

20. The method of claim 17 wherein the first discrete plug extends over, and is coupled to, a drain of a pull-down transistor of the SRAM cell and a drain of a pull-up transistor of the SRAM cell.