Methods of forming 3-D circuits with integrated passive devices

• US 9,236,365 B2
• Filed: 05/12/2014
• Issued: 01/12/2016
• Est. Priority Date: 11/25/2008
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Sanders, Paul W., Petras, Michael F., Ramiah, Chandrasekaram, Jones, Robert E.
• Primary Examiner(s): FERNANDES, ERROL V
• Application Number:
  US14/275,678
• Publication Number:
  US 20140332980A1
• Time in Patent Office: 610 Days
• Field of Search: 257/621, 257/659, 257/724, 257/728, 257684-700, 257773-778, 438/107, 438/667, 438/109
• US Class Current: 1/1
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83365 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/58 : Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/162 : the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0296 : involving a specific disposition of the protective devices
• CPC Class Codes: H01L 27/0629 : in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/00 : Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Claims

1. A method for forming a 3-D integrated circuit, comprising:

forming on separate substrates at least an active device chip, an isolator chip and an integrated passive device (IPD) chip, wherein the substrates of at least two of such chips have one or more conductor filled vias extending there through and wherein at least one of the one or more vias in the IPD chip is coupled to one or more integrated components on the substrate of the IPD chip;

stacking the active device chip, the isolator chip and the IPD chip so that a first via in a first of the at least two chips is aligned with a second via in another of the at least two chips, the first and second vias being two of the conductor filled vias; and

bonding the active device chip, the isolator chip, and the IPD chip together so that the first and second vias are electrically coupled.

2. The method of claim 1, wherein the forming step comprises, forming the active device chip, the isolator chip and the IPD chip with one or more levels of interconnects on first surfaces thereof, wherein at least one of the interconnects in a first one of the chips is coupled during the bonding step with one or more of the conductor filled vias of a second one of the chips which is bonded to the first one of the chips in the bonding step.

3. The method of claim 1, wherein the forming step comprises:

providing an initial substrate having a front face and a rear face;

etching a blind via cavity in the initial substrate extending from the front face toward the rear face;

filling the blind cavity with a conductor having an interior surface proximate a bottom of the cavity;

removing excess conductor from above the blind cavity to expose a first face of the conductor filling the blind cavity;

mounting the initial substrate on a support with the first face toward the support;

removing material from the rear face of the initial substrate thereby providing a thinned substrate having therein a conductor filled via of depth d extending there through and with the first face and the interior surface of the conductor in the cavity exposed; and

removing the support from the thinned substrate.

4. The method of claim 1, wherein the substrate of the isolator chip has a resistivity of 1000 ohm-cm or greater.

5. The method of claim 1, wherein the isolator chip has a thickness of 10 micrometers or larger.

6. The method of claim 1, wherein the substrate of the IPD chip has a resistivity of 1000 ohm-cm or greater.

7. The method of claim 1, wherein the substrate of the active device chip has a first thickness, the substrate of the isolator chip has a second thickness, and the substrate of the IPD chip has a third thickness, and at least one or both of the second and third thickness are at least 2-20 times the first thickness.

8. The method of claim 1, wherein the isolator chip comprises a semiconductor material.

9. The method of claim 1, wherein the IPD chip comprises a semiconductor material.

10. The method of claim 1, wherein the first via is formed in the IPD chip, the second via is formed in the isolator chip and a third via is formed in the active device chip.

11. The method of claim 10, wherein the third via is aligned with the first and second vias.

12. The method of claim 1, the method comprising forming a further interconnect zone located between the substrate of the isolator chip and the substrate of the IPD chip, the further interconnect zone including a lateral conductor between two or more of the conductor filled vias.

13. The method of claim 12, the method comprising forming a circuit element, wherein a first portion of the circuit element is formed in the IPD chip, and a second portion of the circuit element is formed in the further interconnect zone, and wherein the circuit element is selected from an RF transmission line with first and second conductive strips, and an inductor with an inductor loop and a patterned ground plane.

14. The method of claim 12, wherein the further interconnect zone includes a ground plane.

15. The method of claim 12, wherein the further interconnect zone includes an electrical shield.

16. The method of claim 12, wherein the further interconnect zone includes an electromagnetic band gap structure having one or more tuned elements.

17. The method of claim 1 wherein in operation, the isolator chip is operable to improve RF isolation between at least one said integrated component of the IPD chip and at least one circuit element of the active device chip.

18. A method for forming a 3-D integrated circuit, comprising:

providing a first device chip, an isolator chip and a second device chip, each said chip comprising a respective substrate, wherein the substrates of at least two of such chips have one or more conductor filled vias extending there through and wherein at least some of the one or more conductor filled vias in the first or second device chip are coupled to one or more integrated components provided in the first or second device chip;

stacking the first device chip, the isolator chip, and the second device chip so that a first via in a first of the at least two chips is aligned with a second via in another of the at least two chips, the first and second vias being two of the conductor filled vias; and

bonding the first device chip, the isolator chip, and the second chip together so that the first and second vias are electrically coupled and so that the isolator chip provides physical separation between the first device chip and the second device chip.

19. The method of claim 18, wherein at least one of the chips comprises a semiconductor material.

20. The method of claim 18, wherein each of the chips comprises a semiconductor material.

21. A 3-D integrated circuit, comprising:

an active device chip comprising a substrate;

an integrated passive device (IPD) chip comprising a substrate; and

an isolator chip comprising a substrate and having a first side and second side, the first side bonded to the active device chip and the second side bonded to the IPD chip;

wherein the substrates of the IPD chip and the isolator chip have one or more conductor filled vias extending there through and electrically coupled, and

wherein at least one of the one or more vias in the IPD chip is coupled to one or more integrated components located on the opposite side of the substrate of the IPD chip from the isolator chip.

22. The 3-D integrated circuit of claim 21 wherein in operation, the isolator chip is operable to improve RF isolation between at least one said integrated component of the IPD chip and at least one circuit element of the active device chip.

23. A method for forming a 3-D integrated circuit, the method comprising:

providing an active device chip, an isolator chip and an integrated passive device (IPD) chip, each of these chips comprising a respective substrate, wherein the substrate of each of the isolator chip and the IPD chip has one or more conductive vias extending there through, the one or more conductive vias comprising a first via in the IPD chip and a second via in the isolator chip, the first via in the IPD chip being electrically coupled to one or more integrated components on the substrate of the IPD chip; and

stacking and bonding together the active device chip, the isolator chip and the IPD chip so that the isolator chip is between the active device chip and the IPD chip, and the first and second vias are electrically coupled.

24. The method of claim 23 wherein in operation, the isolator chip is operable to improve RF isolation between at least one said integrated component of the IPD chip and at least one circuit element of the active device chip.