Method of maintaining the state of semiconductor memory having electrically floating body transistor

• US 9,236,382 B2
• Filed: 04/16/2015
• Issued: 01/12/2016
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/688,122
• Publication Number:
  US 20150221650A1
• Time in Patent Office: 271 Days
• Field of Search: 365/185.05, 365/185.18
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4067 for memory cells of the bipolar type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Claims

1. A semiconductor memory cell comprising:

a first bipolar device having a floating base region, a collector, and an emitter, and

a second bipolar device having a floating base region, a collector, and an emitter,

wherein the floating base region of said first bipolar device is common to the floating base region of said second bipolar device,

wherein the collector of said first bipolar device is common to the collector of said second bipolar device, and

wherein a state of said memory cell is maintained through a back-bias applied to said collector.

2. The semiconductor memory cell of claim 1, wherein said floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

each said emitter has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said collector has said second conductivity type.

3. The semiconductor memory cell of claim 1, wherein said back-bias applied to said collector is a constant voltage bias.

4. The semiconductor memory cell of claim 1, wherein said back-bias applied to said collector is a periodic pulse of voltage.

5. The semiconductor memory cell of claim 1, further comprising a gate region above said floating base region.

6. The memory cell of claim 1, wherein a maximum potential that can be stored in said floating base region is increased by said applying back bias to the cell, resulting in a relatively larger memory window.

7. The memory cell of claim 1, comprising a fin structure extending from a substrate.

8. A semiconductor memory cell comprising:

a first bipolar device having a floating base region, a collector, and an emitter, and

a second bipolar device having a floating base region, a collector, and an emitter,

wherein the floating base region of said first bipolar device is common to the floating base region of said second bipolar device,

wherein the collector of said first bipolar device is common to the collector of said second bipolar device, and

wherein application of back-bias to said collector results in at least two stable floating base region charge levels.

9. The semiconductor memory cell of claim 8, wherein said floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

each said emitter has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said collector has said second conductivity type.

10. The semiconductor memory cell of claim 8, wherein said back-bias applied to said collector is a constant voltage bias.

11. The semiconductor memory cell of claim 8, wherein said back-bias applied to said collector is a periodic pulse of voltage.

12. The semiconductor memory cell of claim 8, further comprising a gate region above said floating base region.

13. The memory cell of claim 8, wherein a maximum potential that can be stored in said floating base region is increased by said applying back bias to the cell, resulting in a relatively larger memory window.

14. The memory cell of claim 8, comprising a fin structure extending from a substrate.

15. A semiconductor memory cell comprising:

a first bipolar device having a floating base region, a collector, and an emitter, and

a second bipolar device having a floating base region, a collector, and an emitter,

wherein the floating base region of said first bipolar device is common to the floating base region of said second bipolar device, and

wherein the collector of said first bipolar device is common to the collector of said second bipolar device, and

wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell.

16. The semiconductor memory cell of claim 15, wherein said floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

each said emitter has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said collector has said second conductivity type.

17. The semiconductor memory cell of claim 15, wherein said back-bias applied to said collector is a constant voltage bias.

18. The semiconductor memory cell of claim 15, wherein said back-bias applied to said collector is a periodic pulse of voltage.

19. The memory cell of claim 15, wherein a maximum potential that can be stored in said floating base region is increased by said applying back bias to the cell, resulting in a relatively larger memory window.

20. The memory cell of claim 15, comprising a fin structure extending from a substrate.