Semiconductor device

• US 9,236,385 B2
• Filed: 07/21/2014
• Issued: 01/12/2016
• Est. Priority Date: 10/21/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Tsubuku, Masashi, Noda, Kosei, Toyotaka, Kouhei, Watanabe, Kazunori, Harada, Hikaru
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): Gupta, Raj R
• Application Number:
  US14/336,142
• Publication Number:
  US 20140337603A1
• Time in Patent Office: 540 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Claims

1. A memory device comprising:

a memory element comprising a transistor,

the transistor comprising;

a crystalline oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc; and

a gate electrode layer over the channel formation region with an insulating film interposed therebetween,

wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>, and

wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than or equal to 1×

10<sup>−

17</sup> A/μ

m.

2. The memory device according to claim 1, wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>.

3. The memory device according to claim 1, wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%.

4. The memory device according to claim 1, wherein a width of the gate electrode layer is larger than a width of the crystalline oxide semiconductor layer in a channel width direction.

5. The memory device according to claim 1, further comprising:

a first line;

a second line; and

a capacitor,

wherein one of a source and a drain of the transistor is electrically connected to the first line,

wherein the other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor,

wherein the other terminal of the capacitor is electrically connected to the second line.

6. The memory device according to claim 1, wherein the memory device is a DRAM.

7. A processor comprising:

a timing control circuit;

an instruction decoder operationally connected to the timing control circuit;

a register array;

an address logic and buffer circuit operationally connected to the register array;

a data bus interface operationally connected to the register array;

an arithmetic logic unit operationally connected to the register array; and

an instruction register operationally connected to the instruction decoder and the register array,

wherein at least one of the register array and the instruction register comprises the memory device according to claim 1.

8. The processor according to claim 7, wherein the processor is a CPU.

9. A memory device comprising:

a memory element comprising a transistor,

the transistor comprising;

a crystalline oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc;

source and drain electrode layers over the crystalline oxide semiconductor layer;

an insulating film over the source and drain electrode layers and in contact with the crystalline oxide semiconductor layer; and

a gate electrode layer over the channel formation region with the insulating film interposed therebetween,

wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>, and

wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than or equal to 1×

10<sup>−

17</sup> A/μ

m.

10. The memory device according to claim 9, wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>.

11. The memory device according to claim 9, wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%.

12. The memory device according to claim 9, wherein a width of the gate electrode layer is larger than a width of the crystalline oxide semiconductor layer in a channel width direction.

13. The memory device according to claim 9, wherein the memory device is a DRAM.

14. A processor comprising:

a timing control circuit;

an instruction decoder operationally connected to the timing control circuit;

a register array;

an address logic and buffer circuit operationally connected to the register array;

a data bus interface operationally connected to the register array;

an arithmetic logic unit operationally connected to the register array; and

an instruction register operationally connected to the instruction decoder and the register array,

wherein at least one of the register array and the instruction register comprises the memory device according to claim 9.

15. A memory device comprising:

a memory element comprising a transistor,

the transistor comprising;

a first gate electrode layer;

a crystalline oxide semiconductor layer over the first gate electrode layer with a first insulating film interposed therebetween, the crystalline oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc; and

a second gate electrode layer over the channel formation region with a second insulating film interposed therebetween,

wherein the first gate electrode layer and the second gate electrode layer overlap each other with the channel formation region provided therebetween,

wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>, and

wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than or equal to 1×

10<sup>−

17</sup> A/μ

m.

16. The memory device according to claim 15, wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>.

17. The memory device according to claim 15, wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%.

18. The memory device according to claim 15, further comprising:

a first line;

a second line; and

a capacitor,

wherein one of a source and a drain of the transistor is electrically connected to the first line,

wherein the other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor,

wherein the other terminal of the capacitor is electrically connected to the second line.

19. The memory device according to claim 15, wherein the memory device is a DRAM.

20. A processor comprising:

a timing control circuit;

an instruction decoder operationally connected to the timing control circuit;

a register array;

an address logic and buffer circuit operationally connected to the register array;

a data bus interface operationally connected to the register array;

an arithmetic logic unit operationally connected to the register array; and

an instruction register operationally connected to the instruction decoder and the register array,

wherein at least one of the register array and the instruction register comprises the memory device according to claim 15.