Three dimensional NAND device and method of making thereof

• US 9,236,396 B1
• Filed: 11/12/2014
• Issued: 01/12/2016
• Est. Priority Date: 11/12/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Zhang, Yanli, Makala, Raghuveer S., Sharangpani, Rahul, Matamis, George, Zhao, Wei, Koka, Sateesh, Kanakamedala, Senaka
• Primary Examiner(s): Stultz, Jessica
• Assistant Examiner(s): Vu, Vu A
• Application Number:
  US14/539,307
• Time in Patent Office: 426 Days
• Field of Search: 257/316, 438/588, 438/267
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A monolithic three dimensional NAND string includes a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The NAND string also includes a memory film located between the semiconductor channel and the plurality of control gate electrodes and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. The NAND string also includes a plurality of discrete cover silicon oxide segments located between the memory film and each respective clam-shaped portion of the blocking dielectric containing a respective control gate electrode. Each of the plurality of cover silicon oxide segments has curved upper and lower sides and substantially straight vertical sidewalls.

Claims

1. A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, the first material layers comprising a sacrificial material and the second material layers comprising an electrically insulating material;

forming at least one front side opening in the stack;

forming an etch stop layer comprising polysilicon over a sidewall of the at least one front side opening;

forming a memory film comprising a different material than the etch stop layer in the at least one front side opening;

forming a semiconductor channel over the memory film in the at least one front side opening;

forming a back side opening in the stack;

selectively removing the first material layers without removing the second material layers through the back side opening, thereby forming back side recesses between adjacent second material layers and exposing portions of the etch stop layer located in a back portion of the back side recesses;

converting the etch stop layer into a vertically alternating stack of silicon oxide segments and polysilicon segments by oxidizing the exposed portions of the etch stop layer in the back side recesses while the memory material layer remains unchanged, wherein the etch stop layer is a single contiguous layer extending along the sidewall of the at least one front side opening prior to conversion, wherein each silicon oxide segment is an oxidized portion of the etch stop layer after the conversion, and each polysilicon segment is an unoxidized remaining portion of the etch stop layer after the conversion;

forming a blocking dielectric over a sidewall in the back side opening and over exposed surfaces of the second material layers and the silicon oxide segments, the blocking dielectric having a clam-shaped portion in the back side recesses; and

forming a plurality of control gate electrodes, each of the plurality of control gate electrodes is located at least partially in an opening in a respective clam-shaped portion of the blocking dielectric.

2. The method of claim 1, wherein forming the memory film comprises:

forming a charge storage material layer over the etch stop layer in the at least one front side opening; and

forming a tunnel dielectric over the charge storage material layer in the at least one front side opening.

3. The method of claim 1, wherein the blocking dielectric comprises Al₂O₃, and the control gate electrodes comprise tungsten.

4. The method of claim 1, wherein the semiconductor channel comprises a hollow cylinder and further comprising filling the hollow cylinder with an insulating fill material.

5. The method of claim 1, further comprising forming an insulating layer on the substrate prior to forming the stack of first and second material layers.

6. The method of claim 5, wherein forming at least one front side opening comprising removing a portion of the insulating layer, thereby exposing a portion of the surface of the substrate in the memory hole.

7. The method of claim 1, further comprising:

forming a semiconductor liner over the memory film;

etching bottom portions of the semiconductor liner and the memory film to expose a portion of the substrate in the front side opening; and

forming the semiconductor channel over the semiconductor liner in contact with the exposed portion of the substrate in the front side opening.

8. The method of claim 7, wherein:

the semiconductor liner comprises polysilicon or amorphous silicon; and

the semiconductor channel comprises polysilicon or amorphous silicon.

9. The method of claim 8, wherein the first material layers comprise silicon nitride and the second material layers comprise silicon oxide.

10. The method of claim 8, wherein

each silicon oxide segment is located between the memory film and the blocking dielectric;

and

each of the polysilicon segments is located between the memory film and the insulating layer located between the control gate electrodes.

11. The method of claim 1, wherein:

the substrate comprises a silicon substrate;

the monolithic three dimensional NAND string is located in an array of monolithic three dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the three dimensional array of NAND strings is located over another memory cell in a second device level of the three dimensional array of NAND strings; and

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.