FinFET device containing a composite spacer structure
First Claim
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1. A method of forming a FinFET device comprising:
- providing a plurality of semiconductor fins on a surface of a substrate;
forming at least one gate structure orientated perpendicular to and straddling each semiconductor fin of the plurality of semiconductor fins;
providing a composite spacer structure on vertical sidewalls of each gate structure, wherein said composite spacer structure comprises an inner low-k dielectric material portion and an outer nitride material portion and wherein said providing said composite spacer structure comprises forming a dielectric spacer comprising a low-k dielectric material and converting an outer surface of the dielectric spacer into said outer nitride material portion, or depositing a graded spacer profile; and
epitaxially growing a source-side doped semiconductor material portion on an exposed surface of each semiconductor fin and on one side of each gate structure and a drain-side doped semiconductor portion on another exposed surface of each semiconductor fin and on another side of each gate structure.
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Abstract
A composite spacer structure is formed on vertical sidewalls of a gate structure that is formed straddling a semiconductor fin. In one embodiment, the composite spacer structure includes an inner low-k dielectric material portion and an outer nitride material portion.
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Citations
18 Claims
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1. A method of forming a FinFET device comprising:
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providing a plurality of semiconductor fins on a surface of a substrate; forming at least one gate structure orientated perpendicular to and straddling each semiconductor fin of the plurality of semiconductor fins; providing a composite spacer structure on vertical sidewalls of each gate structure, wherein said composite spacer structure comprises an inner low-k dielectric material portion and an outer nitride material portion and wherein said providing said composite spacer structure comprises forming a dielectric spacer comprising a low-k dielectric material and converting an outer surface of the dielectric spacer into said outer nitride material portion, or depositing a graded spacer profile; and epitaxially growing a source-side doped semiconductor material portion on an exposed surface of each semiconductor fin and on one side of each gate structure and a drain-side doped semiconductor portion on another exposed surface of each semiconductor fin and on another side of each gate structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A FinFET device comprising:
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a plurality of semiconductor fins located on a surface of a substrate; at least one gate structure orientated perpendicular to and straddling each semiconductor fin of the plurality of semiconductor fins; a composite spacer structure located on vertical sidewalls of each gate structure, wherein said composite spacer structure comprises an inner low-k dielectric material portion and an outer nitride material portion, wherein said outer nitride material portion comprises a same low-k dielectric material as said inner low-k dielectric material portion and has a higher nitrogen content than said inner low-k dielectric material portion; a source-side doped semiconductor material portion on an exposed surface of each semiconductor fin and on one side of each gate structure; and a drain-side doped semiconductor portion on another exposed surface of each semiconductor fin and on another side of each gate structure. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A FinFET device comprising:
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a plurality of semiconductor fins located on a surface of a substrate; at least one gate structure orientated perpendicular to and straddling each semiconductor fin of the plurality of semiconductor fins; a composite spacer structure located on vertical sidewalls of each gate structure, wherein said composite spacer structure comprises an inner low-k dielectric material portion and an outer doped material portion; a source-side doped semiconductor material portion on an exposed surface of each semiconductor fin and on one side of each gate structure; and a drain-side doped semiconductor portion on another exposed surface of each semiconductor fin and on another side of each gate structure.
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Specification