Display apparatus and method of manufacturing the same

• US 9,236,401 B2
• Filed: 03/03/2014
• Issued: 01/12/2016
• Est. Priority Date: 09/11/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Jae-Neung, Jeong, Yu-Gwang, Kim, Sang-Gab, Bae, Su-Bin, Choi, Shin-Il
• Primary Examiner(s): Kim, Dennis Y
• Application Number:
  US14/195,051
• Publication Number:
  US 20150070643A1
• Time in Patent Office: 680 Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 2201/50 Protective arrangements
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.

Claims

1. A display apparatus comprising:

a backplane panel comprising;

a substrate on which are defined a transistor area and a wiring area;

a thin film transistor in the transistor area of the substrate, and comprising a gate electrode, an active layer, a source electrode and a drain electrode;

an etch prevention layer which is in the transistor area and absent in the wiring area, and covers the active layer, and first and second contact holes defined in the etch prevention layer in the transistor area and through which the active layer is electrically coupled to the source electrode and the drain electrode, respectively;

a first wiring layer in the wiring area of the substrate, the first wiring layer in the wiring area and the gate electrode in the transistor area in different layers;

a first insulating layer which is on the substrate and covers the gate electrode and the first wiring layer, and a third contact hole which is defined in the first insulating layer in the wiring area and exposes the first wiring layer;

a second wiring layer which is on the first insulating layer and in the wiring area of the substrate, and electrically coupled to the first wiring layer via the third contact hole, and

a buffer layer which is on the substrate, between the substrate and the gate electrode in the transistor area, the buffer layer extended to cover the first wiring layer in the wiring area.

2. The display apparatus of claim 1, wherein the etch prevention layer has the same pattern as that of the active layer.

3. The display apparatus of claim 1, wherein the etch prevention layer is directly on the active layer.

4. The display apparatus of claim 1, wherein the second wiring layer is directly on the first insulating layer.

5. The display apparatus of claim 1, further comprising a second insulating layer between the first insulating layer and the second wiring layer.

6. The display apparatus of claim 1, wherein the second wiring layer comprises a same material as that of the source electrode and the drain electrode.

7. The display apparatus of claim 1, further comprising:

a pixel electrode electrically coupled to the source electrode or the drain electrode;

an intermediate layer on the pixel electrode and comprising an organic emission layer; and

a counterpart electrode on the intermediate layer.

8. The display apparatus of claim 1, further comprising:

a first pixel electrode electrically coupled to the source electrode or the drain electrode;

a liquid crystal layer on the first pixel electrode; and

a second pixel electrode on the liquid crystal layer and facing the first pixel electrode.

9. The display apparatus of claim 1, wherein the active layer comprises an oxide semiconductor.

10. A method of manufacturing a display apparatus comprising:

providing a backplane panel, comprising;

forming a first wiring layer in a wiring area of a substrate;

forming a buffer layer to cover the first wiring layer in the wiring area

forming a gate electrode on the buffer layer in a transistor area of the substrate, the first wiring layer in the wiring area and the gate electrode in the transistor area in different layers;

forming a first insulating layer, a semiconductor layer and an etch prevention material layer to cover the gate electrode and the first wiring layer;

etching the semiconductor layer and the etch prevention material layer in the wiring area, to form an active layer and an etch prevention layer on the gate electrode in the transistor area;

simultaneously forming first and second contact holes in the etch prevention layer in the transistor area by patterning the etch prevention layer on the gate electrode, and a third contact hole in the first insulating layer in the wiring area by patterning the first insulating layer on the first wiring layer; and

forming a source electrode and a drain electrode in the transistor area, and a second wiring layer in the wiring area, by forming and patterning a metal layer.

11. The method of claim 10, wherein the etching the semiconductor layer and the etch prevention material layer comprises:

forming the active layer by removing the semiconductor layer in the wiring area, while maintaining the semiconductor layer on the gate electrode in the transistor area, and

forming the etch prevention layer by removing the etch prevention material layer in the wiring area, while maintaining the etch prevention material layer on the gate electrode in the transistor area.

12. The method of claim 11, wherein the semiconductor layer and the etch prevention material layer are simultaneously etched so that the active layer and the etch prevention layer have the same pattern.

13. The method of claim 10, wherein the simultaneously forming the first through third contact holes comprises:

forming the first and second contact holes by patterning the etch prevention layer on the gate electrode, and

forming the third contact hole by patterning the buffer layer and the first insulating layer on the first wiring layer.

14. The method of claim 10, further comprising forming a second insulating layer to cover the etch prevention layer of the transistor area and the first insulating layer of the wiring area.

15. The method of claim 10, wherein the semiconductor layer comprises an oxide semiconductor.

16. The method of claim 10, further comprising forming a second insulating layer on the substrate.

17. The method of claim 16, wherein, in the simultaneously forming the first through third contact holes,

the first and second contact holes are formed to pass through the etch prevention layer and the second insulating layer on the gate electrode, and

the third contact hole is formed to pass through the first and second insulating layers on the first wiring layer.