Semiconductor devices in SiC using vias through N-type substrate for backside contact to P-type layer

• US 9,236,433 B2
• Filed: 10/10/2013
• Issued: 01/12/2016
• Est. Priority Date: 10/10/2013
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Pala, Vipindas, Van Brunt, Edward Robert, Lichtenwalner, Daniel Jenner, Cheng, Lin, Agarwal, Anant Kumar, Palmour, John Williams
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US14/050,727
• Publication Number:
  US 20150102361A1
• Time in Patent Office: 824 Days
• Field of Search: 257/77, 257/E21.054
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/744 Gate-turn-off devices
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type substrate and an epitaxial structure on a front-side of the N-type substrate. The epitaxial substrate includes a P-type layer adjacent to the N-type substrate and one or more additional SiC layers on the P-type layer opposite the N-type substrate. The semiconductor device also includes one or more openings through the N-type substrate that extend from a back-side of the N-type substrate to the P-type layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type substrate.

Claims

1. A semiconductor device comprising:

an N-type Silicon Carbide substrate;

an epitaxial structure on a first side of the N-type Silicon Carbide substrate, the epitaxial structure comprising a P-type Silicon Carbide layer adjacent to the N-type Silicon Carbide substrate;

a plurality of spaced apart highly doped regions formed in the P-type Silicon Carbide layer;

one or more openings through the N-type Silicon Carbide substrate corresponding to the plurality of spaced apart highly doped regions the that extend from a second side of the N-type Silicon Carbide substrate to the P-type Silicon Carbide layer in the epitaxial structure, the second side of the N-type Silicon Carbide substrate being opposite the first side of the N-type Silicon Carbide substrate;

a first contact on the epitaxial structure opposite the N-type Silicon Carbide substrate; and

a second contact on the second side of the N-type Silicon Carbide substrate and within the one or more openings through the N-type Silicon Carbide substrate such that the second contact is in physical and electrical contact with the P-type Silicon Carbide layer;

wherein, in a forward conduction state of the semiconductor device, current flows between the first contact and the second contact through the epitaxial structure.

2. The semiconductor device of claim 1 wherein the one or more openings expose greater than or equal to about 40% of the P-type Silicon Carbide layer but less than all of the P-type Silicon Carbide layer.

3. The semiconductor device of claim 1 wherein the one or more openings expose greater than or equal to about 50% of the P-type Silicon Carbide layer and up to all of the P-type Silicon Carbide layer within an active region of the semiconductor device.

4. The semiconductor device of claim 1 wherein a total thickness of the N-type Silicon Carbide substrate and the epitaxial structure is greater than or equal to about 250 microns.

5. The semiconductor device of claim 1 wherein:

for each opening of the one or more openings through the N-type Silicon Carbide substrate, a corresponding one of the plurality of spaced apart highly doped regions is aligned with the opening and extends from within the P-type Silicon Carbide layer to the P-type Silicon Carbide layer such that the second contact is in physical and electrical contact with the one of the plurality of highly doped regions within the opening.

6. The semiconductor device of claim 5 wherein, for each opening of the one or more openings through the N-type Silicon Carbide substrate, the corresponding one of the plurality of spaced apart highly doped regions is highly doped with Aluminum such that the second contact forms an ohmic contact to the P-type Silicon Carbide layer.

7. The semiconductor device of claim 1 wherein the semiconductor device is an N-channel bipolar device, and the P-type Silicon Carbide layer is an injector layer that injects minority carriers during a forward conduction state of the N-channel bipolar device.

8. The semiconductor device of claim 7 wherein the N-channel bipolar device is one of a group consisting of:

an N-channel Insulated Gate Bipolar Transistor, an N-channel Gate Turn-Off thyristor, and an N-channel thyristor.

9. The semiconductor device of claim 1 wherein the semiconductor device is a PNP Bipolar Junction Transistor (BJT), and the P-type Silicon Carbide layer is a collector of the PNP BJT.

10. The semiconductor device of claim 1 wherein the semiconductor device is a P-channel Metal Oxide Semiconductor Field Effect Transistor, and the P-type Silicon Carbide layer is a drain region of the P-channel Metal Oxide Semiconductor Field Effect Transistor.

11. The semiconductor device of claim 1 wherein the semiconductor device is a bipolar device, the P-type Silicon Carbide layer is an electrically transparent injector layer that injects minority carriers during a forward conduction state of the bipolar device, and the epitaxial structure of the bipolar device further comprises:

an N-type epitaxial layer between the P-type Silicon Carbide layer and the N-type Silicon Carbide substrate;

wherein the one or more openings through the N-type Silicon Carbide substrate extend from the second side of the N-type Silicon Carbide substrate through the N-type epitaxial layer to the P-type Silicon Carbide layer in the epitaxial structure.

12. The semiconductor device of claim 1 wherein the P-type Silicon Carbide layer is directly on the N-type Silicon Carbide substrate.

13. A method of fabricating a semiconductor device, comprising:

providing an epitaxial structure on a first side of an N-type Silicon Carbide substrate, the epitaxial structure comprising a P-type Silicon Carbide layer adjacent to the N-type Silicon Carbide substrate;

forming one or more openings through the N-type Silicon Carbide substrate that extend from a second side of the N-type Silicon Carbide substrate to the P-type Silicon Carbide layer in the epitaxial structure, the one or more openings exposing greater than or equal to about 40% of the P-type Silicon Carbide layer;

forming a plurality of spaced apart highly doped regions in the P-type Silicon Carbide layer through the one or more openings; and

providing a contact on the second side of the N-type Silicon Carbide substrate and within the one or more openings through the N-type Silicon Carbide substrate such that the contact is in physical and electrical contact with the P-type Silicon Carbide layer.

14. The method of claim 13 wherein forming the one or more openings through the N-type Silicon Carbide substrate comprises:

thinning the N-type Silicon Carbide substrate; and

after thinning the N-type Silicon Carbide substrate, etching the N-type Silicon Carbide substrate to form the one or more openings through the N-type Silicon Carbide substrate that extend from the second side of the N-type Silicon Carbide substrate to the P-type Silicon Carbide layer in the epitaxial structure.

15. The method of claim 13 wherein forming the one or more openings through the N-type Silicon Carbide substrate comprises forming the one or more openings through the N-type Silicon Carbide substrate such that the one or more openings expose greater than or equal to about 40% of the P-type Silicon Carbide layer but less than all of the P-type Silicon Carbide layer.

16. The method of claim 13 wherein forming the one or more openings through the N-type Silicon Carbide substrate comprises forming the one or more openings through the N-type Silicon Carbide substrate such that the one or more openings expose greater than or equal to about 50% of the P-type Silicon Carbide layer and up to all of the P-type Silicon Carbide layer within an active region of the semiconductor device.

17. The method of claim 13 wherein a total thickness of the N-type Silicon Carbide substrate and the epitaxial structure is greater than or equal to about 250 microns.

18. The method of claim 13 wherein providing the contact comprises providing the contact on the second side of the N-type Silicon Carbide substrate and within the one or more openings such that the contact is in physical and electrical contact with the one or more of spaced apart highly doped regions within the one or more openings.

19. The method of claim 18 wherein the one or more of spaced apart highly doped regions are highly doped with Aluminum such that the contact forms an ohmic contact to the P-type Silicon Carbide layer.

20. The method of claim 13 wherein the semiconductor device is an N-channel bipolar device, and the P-type Silicon Carbide layer is an injector layer that injects minority carriers during a forward conduction state of the N-channel bipolar device.

21. The method of claim 20 wherein the N-channel bipolar device is one of a group consisting of:

an N-channel Insulated Gate Bipolar Transistor, an N-channel Gate Turn-Off thyristor, or an N-channel thyristor.

22. The method of claim 13 wherein the semiconductor device is a PNP Bipolar Junction transistor (BJT), and the P-type Silicon Carbide layer is a collector of the PNP BJT.

23. The method of claim 13 wherein the semiconductor device is a P-channel Metal Oxide Semiconductor Field Effect Transistor, and the P-type Silicon Carbide layer is a drain region of the P-channel Metal Oxide Semiconductor Field Effect Transistor.

24. The method of claim 13 wherein the semiconductor device is a bipolar device, the P-type Silicon Carbide layer is an electrically transparent injector layer that injects minority carriers during a forward conduction state of the bipolar device, and providing the epitaxial structure on the first side of the N-type Silicon Carbide substrate comprises:

providing an N-type Silicon Carbide layer on the N-type Silicon Carbide substrate; and

providing the P-type Silicon Carbide layer on the N-type Silicon Carbide layer opposite the N-type Silicon Carbide substrate;

wherein the one or more openings through the N-type Silicon Carbide substrate extend from the second side of the N-type Silicon Carbide substrate through the N-type Silicon Carbide layer to the P-type Silicon Carbide layer in the epitaxial structure.

25. The method of claim 13 wherein providing the epitaxial structure on the first side of the N-type Silicon Carbide substrate comprises providing the P-type Silicon Carbide layer directly on the N-type Silicon Carbide substrate.