Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices

• US 9,236,459 B2
• Filed: 09/14/2011
• Issued: 01/12/2016
• Est. Priority Date: 01/23/2009
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Jou, Yeh-Ning, Tu, Shang-Hui, Chang, Jui-Chun, Wu, Chen-Wei
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US13/232,975
• Publication Number:
  US 20120001225A1
• Time in Patent Office: 1,581 Days
• Field of Search: 257/139
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Abstract

Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P⁺ doped drain region is disposed in the high-V N-well. A P⁺ diffused region and an N⁺ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N⁺ doped source region and the other end extending over the insulation region.

Claims

1. An insulated gate bipolar transistor electrostatic discharge (IGBT-ESD) protection device, comprising:

a P-type semiconductor substrate;

a high-voltage N-well formed in the P-type semiconductor substrate;

a patterned insulation region disposed on the high-voltage N-well defining a first active region and a second active region;

a P-type double diffused region disposed in the first active region of the high-voltage N-well;

a single P+ doped drain region disposed in the P-type double diffused region;

a P-body doped region formed in the second active region of the high-voltage N-well, wherein the P-type double diffused region and the P-body doped region are separated with a predetermined distance exposing the high-voltage N-well;

a pair of N+ and P+ doped source regions disposed in the P-body doped region; and

a gate structure disposed on the high-voltage N-well with one end adjacent to the N+ doped source region and with the other end extending over the patterned insulation region, wherein the P-body doped region is separated from the P-type semiconductor substrate only by the high-voltage N-well, and wherein the N+ doped source region is located between the gate structure and the P+ doped source region.

2. The IGBT-ESD protection device as claimed in claim 1, wherein the P-type semiconductor substrate comprises a single crystalline semiconductor substrate, an epitaxial semiconductor substrate, and a silicon-on-insulator (SOI) substrate.

3. The IGBT-ESD protection device as claimed in claim 1, wherein the area of the P+ doped drain region is smaller than the area of the first active region.

4. The IGBT-ESD protection device as claimed in claim 3, wherein the P+ doped drain region comprises a plurality of separated islands.

5. The IGBT-ESD protection device as claimed in claim 1, wherein the P-body doped region is separated from the patterned insulation region.

6. The IGBT-ESD protection device as claimed in claim 1, wherein a depth of the P-body doped region is greater than that of the P-type double diffused region.

7. The IGBT-ESD protection device as claimed in claim 1, wherein the end of the gate structure extends beyond the patterned insulation region without overlapping the N+ doped source region.

8. The IGBT-ESD protection device as claimed in claim 1, further comprising a second patterned insulation region disposed on the high-voltage N-well, wherein the second patterned insulation region is in direct physical contact with the P-body doped region.

9. The IGBT-ESD protection device as claimed in claim 8, wherein the second patterned insulation region is wider than the patterned insulation region.