Analog circuits having improved insulated gate transistors, and methods therefor
First Claim
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1. A circuit, comprising:
- at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and
a bias circuit configured to provide bias currents to the drains of the DDC transistors;
whereineach DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region extending laterally between the source and drain and contacting the source and drain, and a highly doped screening region of a second conductivity type, the highly doped screening region formed below the channel region and extending laterally between the source and drain.
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Abstract
A circuit can include at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the first conductivity type formed below the channel region.
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Citations
23 Claims
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1. A circuit, comprising:
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at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and a bias circuit configured to provide bias currents to the drains of the DDC transistors;
whereineach DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region extending laterally between the source and drain and contacting the source and drain, and a highly doped screening region of a second conductivity type, the highly doped screening region formed below the channel region and extending laterally between the source and drain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A circuit, comprising:
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a plurality of inverting stages coupled to one another in series, an output of a last stage being coupled to an input of a first stage; and each stage comprising at least two deeply depleted channel (DDC) transistors having gates coupled to a stage input, and configured to drive a stage output between two different voltages;
whereineach DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region extending laterally between the source and drain and contacting the source and drain, and a highly doped screening region of a second conductivity type, the highly doped screening region formed below the channel region and extending laterally between the source and drain. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A circuit, comprising:
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at least one varactor element comprising at least a first deeply depleted channel (DDC) transistor having a gate coupled to a first terminal, source and drain coupled to a second terminal, and a body coupled to a third terminal; a first bias circuit coupled to apply a first bias voltage to the third terminal; and a second bias circuit coupled to apply a second bias voltage to the second terminal;
whereineach DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region extending laterally between the source and drain and contacting the source and drain, and a highly doped screening region of a second conductivity type formed below the channel region and extending laterally between the source and drain, and wherein a capacitance between the first and second terminals varies in response to the first and second bias voltages. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification