Stacked integrated circuit with redundancy in die-to-die interconnects

• US 9,236,864 B1
• Filed: 01/17/2012
• Issued: 01/12/2016
• Est. Priority Date: 01/17/2012
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Loh, Siang Poh, Lim, Chooi Pei
• Primary Examiner(s): Huber, Robert
• Application Number:
  US13/352,212
• Time in Patent Office: 1,456 Days
• Field of Search: 438/106, 257/686, 257/106, 326/10, 326/11, 326/16, 326/12
• US Class Current: 1/1
• CPC Class Codes: G11C 29/702 by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H03K 19/003 Modifications for increasing the reliability for protection
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits

Abstract

An integrated circuit (IC) is provided where the IC includes a first die, a second die stacked above the first die, and a plurality of die-to-die interconnects coupling the first die to the second die, where the plurality of die-to-die interconnects includes at least one redundancy die-to-die interconnect. In one implementation, the plurality of die-to-die interconnects includes a plurality of pre-designated die-to-die interconnects, where if a pre-designated die-to-die interconnect of the plurality of pre-designated die-to-die interconnects is defective, then signals intended for transmission via the pre-designated die-to-die interconnect are instead transmitted via the at least one redundancy die-to-die interconnect.

Claims

1. An integrated circuit (IC) comprising:

a first die including a bottom-die redundancy control circuit;

a second die coupled to the first die, the second die including a top-die redundancy control circuit; and

a plurality of die-to-die interconnects coupling the bottom-die redundancy control circuit to the top-die redundancy control circuit, wherein the plurality of die-to-die interconnects comprises a plurality of pre-designated die-to-die interconnects and at least one redundancy die-to-die interconnect,

wherein the bottom-die redundancy control circuit comprises;

a plurality of pre-designated signal paths; and

a redundancy signal path, wherein the redundancy signal path includes a selector coupled to the plurality of pre-designated signal paths,

wherein the selector receives signals received by the plurality of pre-designated signal paths and an additional signal, wherein the additional signal is not a select signal for the selector, further wherein the selector selects a signal from its received signals and outputs the signal to a redundancy die-to-die interconnect of the at least one redundancy die-to-die interconnect,

further wherein the top-die redundancy control circuit comprises;

a plurality of selectors; and

a plurality of decoding logic circuits coupled to the plurality of selectors, wherein each decoding logic circuit of the plurality of decoding logic circuits is coupled to a corresponding selector of the plurality of selectors,

wherein each selector of the plurality of selectors receives a signal from a corresponding pre-designated die-to-die interconnect and a signal from a redundancy die-to-die interconnect of the at least one redundancy die-to-die interconnect, further wherein each selector of the plurality of selectors receives a select signal from a corresponding decoding logic circuit of the plurality of decoding logic circuits.

2. The IC of claim 1, wherein if a pre-designated die-to-die interconnect of the plurality of pre-designated die-to-die interconnects is defective, then signals intended for transmission via the pre-designated die-to-die interconnect are instead transmitted via the at least one redundancy die-to-die interconnect.

3. The IC of claim 1, wherein the plurality of die-to-die interconnects comprises four die-to-die interconnects, wherein three of the four die-to-die interconnects are pre-designated die-to-die interconnects and one of the four die-to-die interconnects is a redundancy die-to-die interconnect.

4. The IC of claim 1, wherein the plurality of die-to-die interconnects comprises a plurality of micro bump interconnects.

5. The IC of claim 1, wherein the IC is a programmable logic device.