Reducing data transition rates between analog and digital chips
First Claim
1. A method for reducing a transition rate in transmitting data between digital and analog chips, the method comprising:
- receiving, by an interface, data from a data source on a first chip;
mapping, by the interface, the data to a transition binary code, the transition binary code comprising a series of 0s and 1s, wherein a number of transitions from a 0 to 1 and from 1 to 0 depends on a probability of a value of the data;
applying an XOR filter to every other bit of the data while mapping the data to the transition binary codes;
transmitting, by the interface, the transition binary code to a second chip; and
applying an XOR filter to every other bit of the transition binary code after transmitting to the second chip.
3 Assignments
0 Petitions
Accused Products
Abstract
Provided are methods and systems for reducing a transition rate in transmitting data between analog and digital chips in Sigma-Delta Modulator (SDM) based Digital to Analog Converters (DACs) and Analog to Digital Converters (ADCs) intended to be used in audio signal processing. An example method may comprise receiving, by a digital chip, SDM binary data, mapping the SDM binary data to transition binary codes, and transmitting the transition binary codes to an analog chip. The mapping can be carried out according to a principle that the more commonly used SDM binary data codes correspond to transition binary data codes that require that fewer transitions occur in the signals between the chips. The methods and systems described provide for lowering the power needed for carrying out the data transmission between digital and analog chips.
13 Citations
21 Claims
-
1. A method for reducing a transition rate in transmitting data between digital and analog chips, the method comprising:
-
receiving, by an interface, data from a data source on a first chip; mapping, by the interface, the data to a transition binary code, the transition binary code comprising a series of 0s and 1s, wherein a number of transitions from a 0 to 1 and from 1 to 0 depends on a probability of a value of the data; applying an XOR filter to every other bit of the data while mapping the data to the transition binary codes; transmitting, by the interface, the transition binary code to a second chip; and applying an XOR filter to every other bit of the transition binary code after transmitting to the second chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A system for reducing a transition rate in transmitting data between digital and analog chips, the system comprising:
an interface configured to; receive data from a data source on a first chip; map the data to a transition binary code, the transition binary code comprising a series of 0s and 1s, wherein a number of transitions from 0 to 1 and from 1 to 0 depends on a probability of a value of the data; apply an XOR filter to every other bit of the data while mapping the data to the transition binary code; and transmit the transition binary code to a second chip, the second chip being configured to apply an XOR filter to every other bit of the transition binary code after receiving the transition binary code from the interface. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
-
19. A non-transitory processor-readable medium having embodied thereon a program being executable by at least one processor to perform a method for reducing a transition rate in transmitting data between digital and analog chips, the method comprising:
-
receiving data from a data source on a first chip; mapping the data to a transition binary code, the transition binary code comprising a series of 0s and 1s, wherein a number of transitions from 0 to 1 and from 1 to 0 depends on a probability of a value of the data; applying an XOR filter to every other bit of the data while mapping the data to the transition binary codes; transmitting the transition binary code to a second chip; and applying an XOR filter to every other bit of the transition binary code after transmitting to the second chip. - View Dependent Claims (20, 21)
-
Specification