Secure modulation and demodulation

• US 9,237,007 B2
• Filed: 12/21/2012
• Issued: 01/12/2016
• Est. Priority Date: 04/07/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Batruni, Roy G.
• Primary Examiner(s): BROWN, CHRISTOPHER J
• Application Number:
  US13/725,829
• Publication Number:
  US 20140146967A1
• Time in Patent Office: 1,117 Days
• Field of Search: 380/46, 380/263, 380/270
• US Class Current: 1/1
• CPC Class Codes: H04K 1/00 Secret communication
• CPC Class Codes: H04L 27/00 Modulated-carrier systems
• CPC Class Codes: H04L 9/0668 producing a non-linear pseudorandom sequence

Abstract

A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signal.

Claims

1. A modulator circuit, comprising:

a feedforward filter;

a processor; and

a feedback filter characterized by a plurality of coefficients;

wherein the processor is configured to apply one or more of a maximum function or a minimum function to a processor input signal to provide a processor output signal to be applied to an input of the feedback filter, the processor input signal being a combination of an output of the feedforward filter and an output of the feedback filter,

wherein one or more of a configuration of the plurality of coefficients or a configuration of the one or more of the maximum function or the minimum function is based upon a key, and

wherein the modulator circuit is comprised in a transmitter, and

wherein the transmitter is configured to share the key with a receiving device to configure the receiving device.

2. The modulator circuit of claim 1, further comprising:

a summer configured to combine the output of the feedforward filter and the output of the feedback filter to provide the processor input signal.

3. The modulator circuit of claim 1 wherein the feedforward filter is configured based upon the key.

4. The modulator circuit of claim 1 wherein the key enables the receiving device to configure a demodulator.

5. The modulator circuit of claim 2, wherein the feedforward filter is from among a plurality of feedforward filters,

wherein the feedback filter is from among a plurality of feedback filters,

wherein the processor input signal is from among a plurality of processor input signals, and

wherein the processor is further configured to apply the one or more of the maximum function or the minimum function to a second processor input signal from among the plurality of processor input signals to select between the processor input signal and the second processor input signal as the processor output signal, the second processor input signal being a combination of an output of a second feedforward filter from among the plurality of feedforward filters and an output of a second feedback filter from among the plurality of feedback filters.

6. The modulator circuit of claim 5, wherein the processor is configured to apply the maximum function to the processor input signal and the second processor input signal.

7. The modulator circuit of claim 5, wherein the processor is further configured to apply the minimum function to the processor input signal and the second processor input signal.

8. The modulator circuit of claim 5, wherein one or more of the feedforward filter, the second feedforward filter, or the feedback filter are configured based upon the key.

9. The modulator circuit of claim 1, wherein the feedback filter comprises:

a plurality of delay stages connected in series;

a plurality of multipliers, each multiplier being coupled to a corresponding delay stage from among the plurality of delay stages; and

a combiner coupled to the plurality of multipliers.

10. The modulator circuit of claim 1, wherein the transmitter comprises a second modulator circuit in series with the modulator circuit, and

wherein the second modulator circuit is configured to perform a nonlinear keying operation.

11. The modulator circuit of claim 10, wherein the transmitter comprises a third modulator circuit in series with the second modulator circuit, and

wherein the third modulator circuit is configured to perform a second nonlinear keying operation.

12. A method performed by a modulator circuit of a transmitter, the method comprising:

configuring a feedforward filter, a feedback filter, and a processor of the modulator circuit using a key;

filtering an input signal with the configured feedback filter;

summing the filtered input signal and a signal output by the configured feedback filter to produce a processor input signal;

performing one or more of a maximum function or a minimum function to the processor input signal to provide a processor output signal; and

sharing the key with a receiving device to configure the receiving device.

13. The method of claim 12, wherein the sharing comprises:

sharing the key with the receiving device to configure a demodulator of the receiving device.

14. The method of claim 12, further comprising:

configuring a second feedforward filter and a second feedback filter using the key;

filtering the input signal with the second configured feedback filter to provide a second filtered input signal;

summing the second filtered input signal and a second signal output by the configured second feedback filter to produce a second processor input signal; and

performing one or more of the maximum function or the minimum function to the second processor input signal to select between the processor input signal and the second processor input signal as the processor output signal.

15. The method of claim 12, wherein the performing comprises:

performing the maximum function to the processor input signal and the second processor input signal.

16. The method of claim 12, wherein the performing comprises:

performing the minimum function to the processor input signal and the second processor input signal.

17. A modulator circuit, comprising:

a plurality of feedforward filters configured to filter an input signal in accordance with a plurality of sets of feedforward coefficients;

a plurality of feedback filters configured to filter a processor output signal in accordance with a plurality of sets of feedback coefficients;

a plurality of summers, each summer from among the plurality of summers being configured to combine an output from a corresponding feedforward filter from among the plurality of feedforward filters and an output from a corresponding feedback filter from among the plurality of feedforward filters to provide a corresponding processor input signal from among a plurality of processor input signals; and

a processor configured to apply one or more of a maximum function or a minimum function to the plurality of processor input signals to select one of the plurality of processor input signals as the processor output signal,

wherein one or more of a configuration of the plurality of sets of feedforward coefficients or the plurality of sets of feedback coefficients or a configuration of the one or more of the maximum function or the minimum function is based upon a key, and

wherein the modulator circuit is comprised in a transmitter, and

wherein the transmitter is configured to share the key with a receiving device to configure the receiving device.