Multiprocessor storage controller

• US 9,239,783 B2
• Filed: 05/14/2013
• Issued: 01/19/2016
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Prins, Douglas A., Olbrich, Aaron K.
• Primary Examiner(s): Yi, David X
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US13/894,326
• Publication Number:
  US 20130262753A1
• Time in Patent Office: 980 Days
• Field of Search: 711/103
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A storage controller has multiple processors, divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In some embodiments, the storage controller operates with a flash memory module, and includes a first processor group, a second processor group and a third processor group, each having one or more processors for handling a different stage of a pipelined execution of host storage commands. With respect to a first host command, a first processor of the first processor group, a first processor of the second processor group, and a first processor of the third processor group comprise a first pipeline, and with respect to a second host command, a second processor of the first processor group, a second processor of the second processor group, and a second processor of the third processor group comprise a second pipeline.

Claims

1. A storage system comprising:

a first and a second flash memory group, each group comprising a plurality of flash memory devices;

a storage controller including a first processor group, a second processor group and a third processor group, each processor group comprising one or more processors for handling a different stage of a pipelined execution of host storage commands;

the first processor group including a host interface circuit coupled to receive a first host command and a second host command from one or more hosts, the first processor group including a first processor and a second processor configured for parallel processing of the first host command and the second host command;

the second processor group including a command processing circuit, the command processing circuit including a first processor and a second processor configured for parallel processing of the first host command and the second host command, the command processing circuit configured to provide the first host command to a first processor of the third processor group and the second host command to a second processor of the third processor group;

wherein the first processor of the third processor group is associated with the first flash memory group and the second processor of the third processor group is associated with the second flash memory group, each such processor of the third processor group being configured for controlling at least some operations of the flash memory group associated therewith;

wherein the storage controller is configured to cause the first and second host commands to be carried out substantially simultaneously.

2. The storage system of claim 1, wherein:

the processors in the first, second and third processor groups are substantially identical processors having different firmware in each group of processors.

3. The storage system as in claim 1, further including one or more buffers;

wherein;

the first processor group includes a third processor operably coupled to the host interface;

the first processor from the first processor group is operably coupled to a first buffer of the one or more buffers that holds information received through the host interface circuit, the first processor from the first processor group including software or hardware control configured to format such information for use by elements of the storage system downstream of the host interface; and

the third processor from the first processor group is operably coupled to a second buffer of the one or more buffers that holds information corresponding to data read from at least one of the first and second flash memory groups, the third processor from the first processor group including software or hardware control configured to format such information for transmission through the host interface.

4. The storage system as in claim 3, wherein:

the second processor group includes a set of one or more processors, each processor in the set of one more processors including software or hardware control configured to directly or indirectly receive information generated by the first processor in the first processor group and directly or indirectly transmit information related to one or more received host commands to one or more processors in the third processor group.

5. The storage system as in claim 3, wherein:

the first processor from the second processor group includes a memory that stores information related to the first host command, but does not store information related to the second host command; and

the second processor from the second processor group includes a memory that stores information related to the second host command, but does not store information related to the first host command.

6. The storage system as in claim 5, wherein:

the second processor group further includes third, fourth, fifth, and sixth processors; and

the storage system is configured to pass information related a third host command from the first processor of the first processor group to a respective processor in the second processor group based at least in part on a current workload of the respective processor compared to current workloads of other processors in the second processor group.

7. The storage system as in claim 1, wherein:

with respect to the first host command, the first processor of the first processor group, the first processor of the second processor group, and the first processor of the third processor group comprise a first pipeline;

with respect to the second host command, the second processor of the first processor group, the second processor of the second processor group, and the second processor of the third processor group comprise a second pipeline; and

wherein processing of the first host command by the first pipeline and processing of the second host command by the second pipeline occur during overlapping periods of time.

8. A method of operating a system including a storage controller configured on a single integrated circuit device, and a plurality of groups of flash memory devices, the storage controller including a first processor group, a second processor group and a third processor group, each processor group comprising one or more processors for handling a different stage of a pipelined execution of host storage commands, the method comprising:

receiving a first host command and performing a task related to the first host command in a first processor of the first processor group, the first host command being received from a first host coupled to the storage controller;

passing information related to the first host command from the first processor directly or indirectly to a second processor, the second processor being part of the second processor group;

performing a task at the second processor related to the first host command and directly or indirectly passing information related to the first host command to a third processor, the third processor being part of the third processor group;

receiving a second host command from a second host coupled to the storage controller at a fourth processor, the fourth processor being part of the first processor group, the first processor and the fourth processor configured for parallel processing of the first host command and the second host command; and

performing a task at the fourth processor related to the second host command;

wherein the operations of performing the task at the first processor and performing the task at the fourth processor occur during overlapping periods of time.

9. The method as in claim 8, wherein:

the first host command includes a first logical address or range;

performing a task at the second processor includes evaluating the first logical address or range;

the third processor is selected based at least in part on the evaluation of the first logical address or range.

10. The method as in claim 9, further including:

initiating at the third processor a flash memory read operation in a first flash memory group, based at least in part on the first logical address or range.

11. The method as in claim 10, further including:

passing information related to the second host command from the fourth processor directly or indirectly to a fifth processor, the fifth processor being part of the second processor group;

passing information related to the second host command from the fifth processor directly or indirectly to a sixth processor, the sixth processor being part of the third processor group; and

initiating at the sixth processor a flash memory read operation in a second flash group, based at least in part on information directly or indirectly received from the fifth processor;

wherein the flash memory read operation in the first flash memory group and the flash memory read operation in the second flash group occur during overlapping periods of time.

12. The method as in claim 11, further including:

passing information related to the first host command from the second processor directly or indirectly to a seventh processor based at least in part on the first logical address or range, the seventh processor being part of the third processor group;

initiating at the seventh processor a flash memory read operation in a third flash group, based at least in part on information directly or indirectly received from the second processor;

wherein the flash memory read operation in the first flash memory group and the flash memory read operation in the third flash group occur during overlapping periods of time.

13. The method as in claim 10, wherein the storage controller further includes a fourth processor group made up of one or more processors, the method further including:

receiving at an eighth processor information relating to data read during the read operation in the first flash memory group, the eighth processor being part of the fourth processor group;

performing at the eighth processor an action relating to the information received at the eighth processor; and

transmitting the data read during the read operation in the first flash memory group to the first host.

14. The method as in claim 13, further including:

receiving at a ninth processor information relating to data read during the read operation in the second flash memory group, the ninth processing being part of the fourth processor group;

performing at the ninth processor performing an action relating to the information received at the ninth processor; and

transmitting the data read during the read operation in the second flash memory group to the second host.

15. The method as in claim 14, wherein:

passing information related to the first host command from the first processor directly or indirectly to the second processor includes passing information to a tenth processor; and

the method further includes;

evaluating at the tenth processor the information related to the first host command; and

selecting the second processor based at least in part on the evaluation at the tenth processor.

16. The method as in claim 15, wherein:

selecting the second processor is based at least in part on an evaluation of a current workload of the second processor relative to current workloads of other processors in the second processor group.

17. The method as in claim 10, further including, prior to completing the read operation in a first flash memory group:

receiving a third host command at the first processor, the third host command including a third logical address or range;

performing at the first processor a task related to the third host command;

passing information related to the third host command from the first processor directly or indirectly to a processor in the second processor group.

18. The method as in claim 8, further including:

passing information related to the second host command from the fourth processor directly or indirectly to a fifth processor, the fifth processor being part of the second processor group;

wherein the second processor and the fifth processor are configured for parallel processing of the first host command and the second host command.

19. The method as in claim 8, wherein:

with respect to the first host command, the first processor of the first processor group, the second processor of the second processor group, and the third processor of the third processor group comprise a first pipeline;

with respect to the second host command, the fourth processor of the first processor group, a fifth processor of the second processor group, and a sixth processor of the third processor group comprise a second pipeline; and

wherein processing of the first host command by the first pipeline and processing of the second host command by the second pipeline occur during overlapping periods of time.