Daisy chain cascading devices

• US 9,240,227 B2
• Filed: 11/08/2006
• Issued: 01/19/2016
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Pyeon, Hong Beom, Kim, Jin-Ki, Oh, HakJune
• Primary Examiner(s): Unelus, Ernest
• Application Number:
  US11/594,564
• Publication Number:
  US 20070109833A1
• Time in Patent Office: 3,359 Days
• Field of Search: 362/232, 365/230.03, 365/233.1, 710/24
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data, address and command information, and control signals to the second device from the first device. The devices coupled in the daisy chain comprise a serial input (SI) and a serial output (SO). Information is input to a device via the SI. The information is output from the device via the SO. The SO of an earlier device in the daisy chain cascade is coupled to the SI of a device later in the daisy chain cascade. Information input to the earlier device via the device'"'"'s SI is passed through the device and output from the device via the device'"'"'s SO. The information is then transferred to the later device'"'"'s SI via the connection from the earlier device'"'"'s SO and the later device'"'"'s SI.

Claims

1. A flash memory system comprising:

a plurality of flash memory devices including at least a first flash memory device and a second flash memory device, the plurality of flash memory devices being connected in a serial arrangement with each other,

the first flash memory device having

a control input port configured to receive a first input enable signal,

a data input port,

a data input circuit coupled to the data input port, the data input circuit being configured to receive the first input enable signal from the control input port through a first control signal path,

a data output port,

a data output circuit coupled to the data output port, the data output circuit being coupled to the control input port through a second control signal path, the second control signal path including

an output control circuit configured to receive the first input enable signal from the control input port and to output a control signal having an active logic level to the data output circuit when the first input enable signal is at an active logic level,

a clock input port, and

a control output port,

the first flash memory device configured

to receive

first input information at the data input port in a predetermined sequence including a p-byte target device address, a q-byte command, and an r-byte address, synchronously with a clock signal received at the clock input port, each of p, q and r being an integer value equal to or greater than 1, and

the first input enable signal having an active logic level at the control input port from an external source device, the data input circuit configured to capture the received first input information when the first input enable signal is at an active logic level to enable the data output circuit in response to the control signal at an active logic level, and to output the captured first input information through the enabled data output circuit as output information from the data output port and

a second input enable signal from the control output port; and

the second flash memory device being associated with a unique device identification number and having

a data input port,

a data output port

a clock input port, and

a control input port,

the second flash memory device configured

to capture the output information of the first flash memory device as second input information at its data input port while the second input enable signal is at the predetermined logic level at the control input port, and

to compare the p-byte target device address included in the captured second input information to the unique device identification number of associated with the second flash memory to determine whether the second flash memory device is a target device.

2. The flash memory system of claim 1 wherein the second input enable signal is the first input enable signal delayed.

3. The flash memory system of claim 1 wherein the second input enable signal is derived from the first input enable signal.

4. The flash memory system of claim 1 wherein the external source device comprises a controller.

5. The flash memory system of claim 1 wherein the external source device comprises another flash memory device.

6. The flash memory system of claim 1 wherein the predetermined sequence begins with the p-byte target device address, followed by the q-byte command, and followed by the r-byte address.

7. The flash memory system of claim 6 wherein the first input information includes input data received after the r-byte address, and the first flash memory device is configured to parse the p-byte target device address of the first input information, and the second flash memory device is configured to parse the p-byte target device address of the second input information to determine whether it is the target device by matching the p-byte target device address with its unique device identification number.

8. The flash memory system of claim 7 wherein each of the first flash memory device and the second flash memory device is further configured to parse the p-byte target device address prior to processing the q-byte command.

9. The flash memory system of claim 8 where each of the first flash memory device and the second flash memory device is further configured to ignore the q-byte command if the p-byte target device address mismatches its unique device identification number.

10. The flash memory system of claim 1, wherein the first flash memory device further includes

a second control input port configured to receive an output enable signal from the external source device, and a second control output port configured to send a second output enable signal, the control input port of the first flash memory device being a first control input port, and the control output port of the first flash memory device being a first control output port;

and

the second flash memory device further includes a second control input port configured to receive the second output enable signal from the first flash memory device, the control input port of the second flash memory device being a first control input port.

11. The flash memory system of claim 1, wherein the clock signal is communicated in a cascading signal to each of the first flash memory device and the second flash memory device.

12. The flash memory system of claim 1, wherein the clock signal is communicated to each of the at least first flash memory device and the second flash memory device in parallel, and an output of the flash memory system is delayed by a predetermined latency.

13. The flash memory system of claim 6 wherein each of the first flash memory device and the second flash memory device further includes

a flash memory bank;

data transfer circuitry configured to receive input data after the r-byte address at the data input port and to transfer the input data to the flash memory bank, and to transfer output data read from the flash memory bank to the data output port; and

control circuitry for controlling write data transfer between the data transfer circuitry and the flash memory bank, and read data transfer between the data transfer circuitry and the data output port.

14. The flash memory system of claim 13 wherein the flash memory bank comprises a NAND flash memory bank.

39. The flash memory system of claim 1 wherein the r-byte address includes an r1-byte column address and an r2-byte row address, each of r1 and r2 being an integer value.

40. The flash memory system of claim 39 wherein r1=2.

41. The flash memory system of claim 39 wherein r2=3.

42. The flash memory system of claim 41 wherein the row address includes a bank address.

43. The flash memory system of claim 1 wherein the second flash memory device further includes a control output port configured to send the output information and a third input enable signal to an external target device.

44. The flash memory system of claim 10 wherein the output control circuit is configured to receive the output enable signal and output the control signal having an active logic level when the output enable signal is at an active logic level.

15. A semiconductor memory device comprising:

memory;

a control input port configured to receive an input enable signal;

a clock input port for receiving a clock signal;

a data input port configured to receive input information in a predetermined sequence including a p-byte target device address, a q-byte command, and an r-byte address, synchronously with the clock signal, each of the p, q and r being an integer value equal to or greater than 1,

a data input circuit coupled to the data input port, the data input circuit being configured to receive the input enable signal from the control input port through a first control signal path, the data input circuit configured to capture the received input information when the input enable signal is at an active logic level,

a data output port,

a data output circuit coupled to the data output port, the data output circuit being coupled to the control input port through a second control signal path, the second control signal path including

an output control circuit configured to receive the input enable signal from the control input port and to output a control signal having an active logic level to the data output circuit when the input enable signal is at an active logic level, the data output circuit being enabled in response to the control signal at an active logic level, the data output port outputting the captured input information through the enabled data output circuit;

a unique device identification number, the unique device identification number being used to determine whether the semiconductor memory device possessing the unique device identification number is to be responsive to the q-byte command;

control circuitry for determining whether the p-byte target device address relates to the unique device identification number, and providing a determination result;

data transfer circuitry configured to respond to the q-byte command in response to the determination result and to provide one of read data and the input information as output data from the data output port.

16. The semiconductor memory device of claim 15 wherein the memory comprises a plurality of memory banks.

17. The semiconductor memory device of claim 15 wherein the output data contains the p-byte target device address;

and the control circuitry is configured to control data transfer between the data transfer circuitry and the memory, and between the data transfer circuitry and the data output port.

18. The semiconductor memory device of claim 17, wherein the data transfer occurs at a double data rate in response to the rising and falling edges of the clock signal.

19. The semiconductor memory device of claim 17, wherein the input information includes serial information, and the data transfer circuitry is further configured to convert serial write data of the serial information into parallel write data and to transfer the parallel write data to the memory.

20. The semiconductor memory device of claim 19, wherein the data transfer circuitry is further configured to convert parallel read data from the memory into serial read data.

21. The semiconductor memory device of claim 20, wherein the control circuitry is configured to receive executable instructions corresponding to the q-byte command to control the transfer of serial write data to the memory, and the transfer of the serial read data from the memory.

22. The semiconductor memory device of claim 19, wherein the control circuitry is programmed with executable instructions to parse the p-byte target device address of the serial information and to control the transfer of the parallel write data to a location in the memory identified in the r-byte address of the captured input information.

23. The semiconductor memory device of claim 15, wherein the memory, the data transfer circuitry and the control circuitry are located within a single package having a one-side pad architecture.

24. The semiconductor memory device of claim 15, wherein the memory comprises a non-volatile memory bank.

25. The semiconductor memory device of claim 24, wherein the non-volatile memory bank comprises a flash memory bank.

26. The semiconductor memory device of claim 24, wherein the non-volatile memory bank comprises a NAND flash memory bank.

34. The semiconductor memory device of claim 15, wherein the control circuitry is configured to determine whether the p-byte target device address matches the unique device identification number to provide the determination result.

37. The semiconductor memory device of claim 15, wherein the control input port is a first control input port, and the semiconductor memory device further includes

a second control input port distinct from the data input port configured to receive an output enable signal for enabling the data output port to provide the output data.

45. The semiconductor memory device of claim 37 wherein the output control circuit is configured to receive the output enable signal and output the control signal having an active logic level when the output enable signal is at an active logic level.

27. A memory system having a plurality of memory devices that are serially connected, the plurality of memory devices comprising at least first and second memory devices, an access to the first and the second memory devices being determined by device identification,

the first memory device having

(a) memory,

(b) a first unique device identifier,

(c) a control input port configured to receive an input enable signal,

(d) a data input port,

(e) a data input circuit coupled to the data input port, the data input circuit being configured to receive the input enable signal from the control input port through a first control signal path,

(f) a data output port,

(g) a data output circuit coupled to the data output port, the data output circuit being coupled to the control input port through a second control signal path, the second control signal path including

an output control circuit configured to receive the input enable signal from the control input port and to output a control signal having an active logic level to the data output circuit when the input enable signal is at an active logic level,

(h) a control output port,

(i) a clock input port,

the data input circuit being configured to capture input information in a predetermined sequence including a p-byte target device address, a q-byte command, and r-byte address, synchronously with a clock signal received at the clock input port, at the data input port from an external source device when the input enable signal is at an active logic level, each of p, q and r being an integer value equal to or greater than 1, and

the data output circuit being enabled in response to the control signal at an active logic level to send one of the input information in response to the input enable signal driven at an active logic level and read data as output data from the data output port, and to send the input enable signal from the control output port, and further configured to process the q-byte command if the first memory device is identified as a target device when the p-byte target device address relates to the first unique device identifier of the first memory device;

and

the second memory device having

(a) a second unique device identifier,

(b) a data input port, in communication with the data output port of the first memory device, and

(c) a data output port,

(d) a control input port,

(e) a clock input port

the second memory device being configured to capture the input information from the first memory device at the data input port of the second memory device in response to the input enable signal provided by the control output port of the first memory device which is received at the control input port of the second memory device while the input enable signal is driven at the logic level, and to process the captured input information if the second memory device is identified as the target device when the p-byte target device address relates to the second unique device identifier of the second memory device.

28. The memory system of claim 27 wherein the external source device comprises a controller.

29. The memory system of claim 27 wherein the external source device comprises a memory device.

30. The memory system of claim 27 wherein the second memory device is further configured to send at least the output data received at its data input port to an external target device through its data output port.

31. The memory system of claim 27 wherein each of the at least first and second memory devices of the plurality of memory devices is further configured to bypass the q-byte command without processing if neither the first memory device nor the second memory device is identified as the target device when the p-byte target device address is unrelated to either of the first unique device identifier and the second unique device identifier.

32. The memory system of claim 27 wherein the memory of the first memory device comprises a flash memory.

33. The memory system of claim 27 wherein the memory of the first memory device comprises a NAND flash memory.

35. The memory system of claim 27, wherein:

the first memory device is configured to determine whether the p-byte target device address matches the first unique device identifier of the first memory device to identify the first memory device as the target device; and

the second memory device is configured to determine whether the p-byte target device address matches the second unique device identifier of the second memory device to identify the second memory device as the target device.

36. The memory system of claim 31, wherein:

the first memory device is configured to determine whether the p-byte target device address matches the first unique device identifier of the first memory device, the q-byte command being bypassed if the p-byte target device address mismatches the first unique device identifier; and

the second memory device is configured to determine whether the p-byte target device address matches the second unique device identifier of the second memory device, the q-byte command being bypassed if the p-byte target device address mismatches the second unique device identifier.

38. The memory system of claim 27, wherein the control input port is a first control input port, and the first memory device further includes

a second control input port distinct from the data input port configured to receive an output enable signal for enabling the data output port to provide the output data.

46. The memory system of claim 27 wherein the output control circuit is configured to receive the output enable signal and output the control signal having an active logic level when the output enable signal is at an active logic level.

47. An apparatus having a plurality of devices configured in a daisy chain cascade arrangement, the apparatus comprising:

a first memory device having;

(a) memory,

(b) a first input for receiving address information associated with a memory location in the memory,

(c) a first control input for receiving a first input enable signal that is used to enable the first input to receive the address information,

(d) a second control input for receiving a first output enable signal set to a first logic level for a duration of time,

(e) a first output for providing first output data contained in the memory location in the memory in response to the first output enable signal being at the first logic level for the duration of time,

(f) a first control output for providing a second input enable signal in response to the first input enable signal,

(g) a second control output for providing a second output enable signal in response to the first output enable signal, the second output enable signal being at the first logic level for the duration of time; and

a second memory device having;

(a) a first control input for receiving the second input enable signal from the first memory device,

(b) a first input for receiving the first output data provided from the first memory device in response to the received second input enable signal,

(c) a second control input for receiving the second output enable signal from the first memory device,

(d) a first output configured to output second output data to a subsequent device in response to the received second output enable signal being at the first logic level for the duration of time,

the second output data being one of the first output data received by the first input of second memory device and data provided by the second memory device.

48. A method for reading data from a plurality of devices configured in a daisy chain cascade arrangement, the method comprising:

inputting into a first input of a first memory device, address information associated with a memory location of memory contained in the first memory device;

inputting into a first control input of the first memory device, a first input enable signal that is used to enable the address information to be input to the first input of the first memory device;

outputting from a first control output of the first memory device, a second input enable signal;

receiving at a first control input of a second memory device, the second input enable signal;

accessing data in memory contained in the first memory device at the memory location;

inputting into a second control input of the first memory device, a first output enable signal set to a first logic level for a duration of time;

outputting from a first output of the first memory device, the accessed data in response to the first output enable signal being at the first logic level for the duration of time;

outputting from a second control output of the first memory device, a second output enable signal set to the first logic level for the duration of time;

receiving into a first input of the second memory device, the accessed data provided from the first output of the first memory device;

receiving into a second control input of the second memory device, the second output enable signal; and

providing output data from a first output of the second memory device to a subsequent device in response to the second output enable signal, the output data being one of the accessed data and data provided by the second memory device.

49. An apparatus comprising:

means for inputting, into a first input of a first memory device, address information associated with a memory location of memory contained in the first memory device during an active logic state of an input enable signal;

means for accessing data in memory contained in the first memory device at the memory location; and

means for coupling a first output of the first device to a first input of a second memory device to allow the accessed data to be transferred from the first memory device to the second memory device in response to an output enable signal set to an active logic state for a duration of time, the second memory device having a first output coupled to the first input of the second memory device through a data transfer path, the data transfer path being configured to transfer the data received by the first input to the first output of the second memory device, the first output of the second memory device being configured to transfer the data as read data to a subsequent device in response to an active logic state of the input enable signal.

50. A memory system for providing read data comprising:

a memory controller for providing address information corresponding to a memory location, an input enable signal and an output enable signal set to a first logic level for a duration of time, the memory controller configured for receiving the read data stored in the memory location;

a first memory device having a first input and a first output, the first input receiving the address information in response to the input enable signal, and the first output providing first output data corresponding to the address information in response to the output enable signal being at the first logic level for the duration of time;

a second memory device having a first input connected to the first output of the first device for receiving the first output data, the first output of the second memory device being configured to output second output data as the read data in response to the output enable signal being at the first logic level for the duration of time, the second output data being one of the first output data provided by the first memory device and data provided by the second memory device.