Method of operating channel buffer block and devices including the channel buffer block
First Claim
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1. A column driver integrated circuit (IC) having a channel buffer block, wherein the channel buffer block comprises:
- a first differential amplifier having a first bias circuit configured to generate a first bias current inversely proportional to a first bias voltage and a first transistor pair configured to amplify a difference between input voltages using the first bias current;
a second differential amplifier having a second bias circuit configured to generate a second bias current proportional to a second bias voltage and a second transistor pair configured to amplify the difference between the input voltages using the second bias current;
a first coupling capacitor configured to decrease the first bias voltage using a first control voltage during a slewing interval; and
a second coupling capacitor configured to increase the second bias voltage using a second control voltage during the slewing interval.
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Abstract
A method of operating a channel buffer block is provided. The method includes changing bias voltages applied to bias lines in an input stage included in the channel buffer block using a coupling effect of coupling capacitors during a slewing interval and increasing bias currents in the input stage using input voltages and changed bias voltages.
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Citations
16 Claims
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1. A column driver integrated circuit (IC) having a channel buffer block, wherein the channel buffer block comprises:
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a first differential amplifier having a first bias circuit configured to generate a first bias current inversely proportional to a first bias voltage and a first transistor pair configured to amplify a difference between input voltages using the first bias current; a second differential amplifier having a second bias circuit configured to generate a second bias current proportional to a second bias voltage and a second transistor pair configured to amplify the difference between the input voltages using the second bias current; a first coupling capacitor configured to decrease the first bias voltage using a first control voltage during a slewing interval; and a second coupling capacitor configured to increase the second bias voltage using a second control voltage during the slewing interval. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An image processing system comprising:
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a column driver integrated circuit (IC) having a channel buffer block; a timing controller configured to control operation of the column driver IC; and a processor configured to control operation of the timing controller, wherein the channel buffer block comprises; a first differential amplifier having a first bias circuit configured to generate a first bias current inversely proportional to a first bias voltage and a first transistor pair configured to amplify a difference between input voltages using the first bias current; a second differential amplifier having a second bias circuit configured to generate a second bias current proportional to a second bias voltage and a second transistor pair configured to amplify the difference between the input voltages using the second bias current; a first coupling capacitor configured to decrease the first bias voltage using a first control voltage during a slewing interval; and a second coupling capacitor configured to increase the second bias voltage using a second control voltage during the slewing interval. - View Dependent Claims (13, 14, 15, 16)
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Specification