Apparatus having indications of memory cell density and methods of their determination and use

• US 9,240,240 B2
• Filed: 11/29/2011
• Issued: 01/19/2016
• Est. Priority Date: 11/29/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F., Sarin, Vishal
• Primary Examiner(s): Yang, Han
• Application Number:
  US13/306,227
• Publication Number:
  US 20130135926A1
• Time in Patent Office: 1,512 Days
• Field of Search: 365/185.03, 365/200, 365/201, 365/185.18
• US Class Current: 1/1
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Methods and apparatus utilizing indications of memory cell density facilitate management of memory density of a memory device. By permitting each of a plurality of portions of a memory array of the memory device to be assigned a corresponding memory cell density determined through an evaluation of those portions of the memory array, better performing portions of the memory array may not be hindered by lesser performing portions of the memory array.

Claims

1. An apparatus, comprising:

an array of memory cells comprising a plurality of series-connected strings of memory cells; and

a control logic to control access to the array of memory cells;

wherein indications of memory cell density for a plurality of portions of the array of memory cells are stored in the apparatus;

wherein two or more indications of memory cell density correspond to a particular series-connected string of memory cells of the plurality of series-connected strings of memory cells; and

wherein each indication of memory cell density corresponding to the particular series-connected string of memory cells corresponds to a different respective set of memory cells of the particular series-connected string of memory cells.

2. The apparatus of claim 1, wherein each memory cell of the particular series-connected string of memory cells corresponds to a corresponding one of the indications of memory cell density.

3. The apparatus of claim 1, wherein each of the indications of memory cell density corresponding to the particular series-connected string of memory cells is independent of other of the indications of memory cell density corresponding to the particular series-connected string of memory cells.

4. The apparatus of claim 1, wherein the indications of memory cell density are stored in a location selected from the array of memory cells and a control register of the control logic.

5. The apparatus of claim 1, wherein the indications of memory cell density are stored in the array of memory cells, and wherein the control logic is further configured to read the indications of memory cell density from the array of memory cells as part of an initialization process of the apparatus.

6. The apparatus of claim 1, wherein the indications of memory cell density comprise three or more different values.

7. The apparatus of claim 1, wherein a number of the indications of memory cell density is equal to a number of the plurality of portions of the array of memory cells.

8. The apparatus of claim 1, wherein at least one of the indications of memory cell density corresponds to more than one of the portions of the array of memory cells.

9. The apparatus of claim 1, wherein each of the indications of memory cell density represents both a number of data states to which each memory cell of the corresponding portion of memory cells can be programmed and a number of memory cells to be used for each grouping of memory cells for mapping of data to the corresponding portion of the plurality of portions of the memory array.

10. The apparatus of claim 1, wherein each portion of the plurality of portions of the array of memory cells is selected from the group consisting of a plane of the array of memory cells, an erase block of the array of memory cells, a physical row of the array of memory cells, a logical row of the array of memory cells, or some combination thereof.

11. The apparatus of claim 1, wherein the control logic is further configured to select an algorithm for writing data to a particular portion of the array of memory cells in response to the indication of memory cell density for that particular portion of the array of memory cells.

12. An apparatus, comprising:

an array of memory cells comprising a plurality of series-connected strings of memory cells; and

a control logic to control access to a particular memory cell of a particular series-connected string of memory cells of the plurality of series-connected strings of memory cells using a first indication of memory cell density corresponding to the particular memory cell and to control access to a different memory cell of the particular series-connected string of memory cells using a second indication of memory cell density corresponding to the different memory cell;

wherein the first indication of memory cell density is independent of the second indication of memory cell density.

13. The apparatus of claim 12, wherein each memory cell of the particular series-connected string of memory cells corresponds to a corresponding indication of memory cell density that is independent of an indication of memory cell density corresponding to any other memory cell of the particular series-connected sting of memory cells.

14. The apparatus of claim 12, wherein at least one of the first indication of memory cell density and the second indication of memory cell density corresponds to a memory cell in more than one string of series-connected strings of memory cells of the plurality of strings of memory cells.

15. The apparatus of claim 14, wherein the first indication of memory cell density and the second indication of memory cell density correspond, respectively, to a first logical row of memory cells of the array of memory cells and a second logical row of memory cells of the array of memory cells.

16. The apparatus of claim 12, wherein access comprises an operation selected from the group consisting of reading data and writing data.

17. An apparatus, comprising:

a memory device comprising an array of memory cells and storing indications of memory cell density for a plurality of portions of the array of memory cells; and

a processor to control access to the memory device, wherein the processor is configured to obtain the indications of memory cell density from the memory device;

wherein the array of memory cells comprises a plurality of series-connected strings of memory cells; and

wherein two or more indications of memory cell density correspond to a particular series-connected string of memory cells of the plurality of series-connected strings of memory cells; and

wherein each indication of memory cell density corresponding to the particular series-connected string of memory cells corresponds to a different respective set of memory cells of the particular series-connected string of memory cells.

18. The apparatus of claim 17, wherein the processor is configured to obtain the indications of memory cell density as part of an initialization process of the memory device.

19. The apparatus of claim 17, wherein the processor is configured to obtain the indications of memory cell density by querying the memory device.

20. The apparatus of claim 17, wherein the particular series-connected string of memory cells spans two or more of the portions of the array of memory cells.

21. The apparatus of claim 20, wherein the particular series-connected string of memory cells spans a number of the portions of the array of memory cells equal to a number of memory cells of the particular series-connected string of memory cells.

22. The apparatus of claim 17, wherein the indications of memory cell density for the plurality of portions of the array of memory cells comprise indications having at least three different values.

23. The apparatus of claim 17, wherein the processor is further configured to determine a corresponding memory cell density for each of the plurality of portions of the array of memory cells.

24. The apparatus of claim 23, wherein the processor is further configured to determine the corresponding memory cell density for each of the plurality of portions of the array of memory cells to satisfy a particular set of reliability criteria.

25. The apparatus of claim 24, wherein the particular set of reliability criteria comprises programming and reading data values for a particular number of program/erase cycles, obtaining a particular period of data retention, maintaining a particular error rate, operating at a particular temperature range, operating for a particular number of hours, and receiving a particular supply voltage.

26. The apparatus of claim 23, wherein the processor is further configured to determine the corresponding memory cell density for the particular set of reliability criteria for each of the plurality of portions of the array of memory cells for at least one condition selected from the group consisting of periodically, in response to a particular number of portions of the memory device being marked as defective, and in response to a user command.

27. The apparatus of claim 23, wherein the processor is further configured to determine a corresponding memory cell density for the particular set of reliability criteria for one or more other portions of the array of memory cells as a function of memory cell density for one or more of the plurality of portions of the array of memory cells.

28. A method of operating a memory device, comprising:

evaluating disturb mechanisms for a plurality of portions of an array of memory cells of the memory device;

determining a corresponding memory cell density for each of the plurality of portions of the array of memory cells in response to evaluating the disturb mechanisms; and

storing indications of the determined memory cell densities for each of the plurality of portions of the array of memory cells to the memory device.

29. The method of claim 28, wherein determining a corresponding memory cell density for each of a plurality of portions of an array of memory cells comprises determining the corresponding memory cell density for a particular set of reliability criteria for each of the plurality of portions of an array of memory cells.

30. The method of claim 29, wherein evaluating disturb mechanisms for a plurality of portions of an array of memory cells comprises:

writing data to the plurality of portions of the array of memory cells;

reading the data from the plurality of portions of the array of memory cells; and

comparing the data read from the plurality of portions of the array of memory cells to the data written to the plurality of portions of the array of memory cells.

31. The method of claim 28, wherein storing indications of the determined memory cell densities for the plurality of portions of the array of memory cells to the memory device comprises storing information representative of both a number of data states to which each memory cell of a corresponding portion of the array of memory cells can be programmed and a number of memory cells to be used for grouping memory cells for mapping data to the memory device.

32. The method of claim 29, wherein determining the memory cell densities for the particular set of reliability criteria comprises determining the memory cell densities for criteria selected from the group consisting of programming and reading data values for a particular number of program/erase cycles, obtaining a particular period of data retention, maintaining a particular error rate, operating at a particular temperature range, operating for a particular number of hours, and receiving a particular supply voltage.

33. A method of operating an array of memory cells, comprising:

writing data to a plurality of portions of an array of memory cells;

reading the data from the plurality of portions of the array of memory cells;

comparing the data read from the plurality of portions of the array of memory cells to the data written to the plurality of portions of the array of memory cells;

determining a corresponding memory cell density for a particular set of reliability criteria for each of the plurality of portions of the array of memory cells in response to comparing the data; and

determining a corresponding memory cell density for the particular set of reliability criteria for each of one or more other portions of the array of memory cells without comparing data read from the one or more other portions of the array of memory cells to data written to the one or more other portions of the array of memory cells.

34. The method of claim 33, wherein writing data to a plurality of portions of an array of memory cells and reading the data from the plurality of portions of the array of memory cells is repeated for more than one iteration.

35. The method of claim 34, further comprising erasing the data from the plurality of portions of the array of memory cells after reading the data from the plurality of portions of the array of memory cells.

36. The method of claim 34, wherein the data written to the plurality of portions of the array of memory cells is different for a subsequent iteration.

37. The method of claim 33, wherein determining a corresponding memory cell density for the particular set of reliability criteria for each of one or more other portions of the array of memory cells further comprises assigning a corresponding memory cell density to one of the other portions of the array of memory cells as a function of the memory cell density of one of the plurality of portions of the array of memory cells.

38. An apparatus, comprising:

an array of memory cells, wherein;

a first group of memory cells of the array of memory cells are assigned a first memory cell density; and

a second group of memory cells of the array of memory cells are assigned a second memory cell density different from the first memory density,

wherein a memory cell of the first group of memory cells is connected in series with a memory cell of the second group of memory cells.

39. The apparatus of claim 38, wherein the first group of memory cells comprises a first physical row of memory cells and wherein the second group of memory cells comprises a second physical row of memory cells.

40. The apparatus of claim 38, wherein the first group of memory cells comprises a first logical row of memory cells and wherein the second group of memory cells comprises a second logical row of memory cells.

41. The apparatus of claim 38, wherein the first group of memory cells comprises a physical row of memory cells and wherein the second group of memory cells comprises a logical row of memory cells.

42. A method of operating an array of memory cells, comprising:

individually determining memory cell density for each of a plurality of portions of the array of memory cells; and

assigning the corresponding individually determined memory cell density to each of the plurality of portions of the array of memory cells;

wherein a memory cell of a particular portion of the plurality of portions of the array of memory cells is connected in series with a memory cell of a different portion of the plurality of portions of the array of memory cells.

43. A method of operating an array of memory cells, comprising:

storing a corresponding indication of memory cell density for each of a plurality of portions of the array of memory cells; and

operating each of the plurality of portions of the array of memory cells in accordance with its corresponding indication of memory cell density;

wherein a memory cell of one of the plurality of portions of the array of memory cells having a particular corresponding indication of memory cell density is connected in series with a memory cell of another one of the plurality of portions of the array of memory cells having a different corresponding indication of memory cell density.

44. The method of claim 43, wherein the stored indications of memory cell density correspond to the plurality of portions of the array of memory cells in a one-to-one correspondence.

45. The method of claim 43, wherein each of a number of the stored indications of memory cell density correspond to more than one of the plurality of portions of the array of memory cells.