Method of making a semiconductor device package

• US 9,240,348 B2
• Filed: 08/22/2014
• Issued: 01/19/2016
• Est. Priority Date: 10/21/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Hsueh-An
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US14/465,942
• Publication Number:
  US 20140363968A1
• Time in Patent Office: 515 Days
• Field of Search: 438/624
• US Class Current: 1/1
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00571 Avoid or control under-cutting
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A method of forming a semiconductor device package includes bonding a front surface of a first substrate to a second substrate, and thinning a back surface of the first substrate. The method includes depositing and patterning a dielectric layer on the thinned back surface of the first substrate, and etching the first substrate after the depositing and the patterning of the dielectric layer are performed to form a through silicon via to enable electrical connection with a first level metal of the first substrate. The method includes depositing an isolation layer to line the through silicon via is formed, and etching the isolation layer at the bottom of the through silicon via. The method includes depositing a conductive layer to line the through silicon via after the isolation layer at the bottom of the through silicon via is etched, and deposited a copper film over the conductive layer.

Claims

1. A method of forming a semiconductor device package, the method comprising:

bonding a front surface of a first substrate to a second substrate;

thinning a back surface of the first substrate;

depositing and patterning a dielectric layer on the thinned back surface of the first substrate;

etching the first substrate after the depositing and the patterning of the dielectric layer are performed to form a through silicon via to enable making an electrical connection with a first level metal of the first substrate;

depositing an isolation layer to line the through silicon via;

etching the isolation layer at the bottom of the through silicon via; and

depositing a conductive layer to line the through silicon via after the isolation layer at the bottom of the through silicon via is etched; and

depositing a copper film over the conductive layer.

2. The method of claim 1, wherein the conductive layer includes a copper-barrier sub-layer and a copper-seed sub-layer.

3. The method of claim 1, wherein the through silicon via makes direct contact with the first level metal.

4. The method of claim 1, wherein the through silicon via makes contact with a polysilicon gate structure and makes the electrical connection with the first level metal through the polysilicon gate structure and a contact plug between the polysilicon gate structure and the first level metal.

5. The method of claim 1, wherein the copper film is plated on the conductive layer and partially fills the through silicon via.

6. The method of claim 5, further comprising:

depositing a polymer layer, wherein the polymer layer fills the remaining space of the through silicon via not filled by the copper film.

7. A method of making a semiconductor device package, the method comprising:

bonding a first substrate to a second substrate;

forming a through silicon via opening in the first substrate extending from a first surface of the first substrate to a first-level metal structure of the first substrate,

lining the through silicon via opening with an isolation layer and a conductive layer,

filling at least a portion of the through silicon via opening with a copper layer on the conductive layer to form redistribution layer extending laterally along the first surface of the first substrate beyond the through silicon via opening, and

electrically connecting the conductive layer to the first-level metal structure through a gate structure and at least one contact plug.

8. The method of claim 7, wherein forming the through silicon via opening comprises forming an opening in a gate dielectric layer, wherein the gate dielectric layer is between the gate structure and the first substrate.

9. The method of claim 7, further comprising forming a micro-electrical-mechanical system (MEMS) device in the second substrate.

10. The method of claim 7, further comprising forming a connection structure electrically connected to the redistribution layer.

11. The method of claim 10, wherein forming the connection structure comprises forming at least one of a solder bump or a copper pillar.

12. The method of claim 7, further comprising bonding a wafer to the first substrate, wherein the second substrate is between at least a portion of the wafer and at least a portion of the first substrate.

13. The method of claim 12, wherein bonding the wafer to the first substrate comprises forming at least one opening in the second substrate and bonding the wafer to the first substrate through the at least one opening.

14. The method of claim 12, wherein bonding the wafer to the first substrate comprises:

forming at least one first bonding pad on the first substrate;

forming at least one second bonding pad on the wafer; and

bonding each first bonding pad of the at least one first bond pad to a corresponding second bonding pad of the at least one second bonding pad by metal diffusion.

15. A method of making semiconductor device package, the method comprising:

bonding a first substrate to a second substrate;

forming a through silicon via in the first substrate, wherein the through silicon via extends from a first surface of the first substrate to physically contact a polysilicon gate structure of the first substrate, and the through silicon via is lined with an isolation layer and a conductive layer; and

forming an interconnect structure on the first substrate, wherein the interconnect structure is between the polysilicon gate structure and the second substrate, and the polysilicon gate structure is connected to the interconnect structure on an opposite side of the polysilicon gate structure from the through silicon via.

16. The method of claim 15, further comprising forming at least one contact plug, wherein the at least one contact plug electrically connects the polysilicon gate structure to the interconnect structure.

17. The method of claim 15, wherein forming the through silicon via comprises etching a portion of the polysilicon gate structure.

18. The method of claim 15, wherein forming the through silicon via comprises:

forming an opening in the first substrate; and

partially filling the opening with a polymer layer.

19. The method of claim 18, wherein forming the through silicon via further comprises forming a conductive layer in the opening, wherein the conductive layer extends across a surface of the first substrate opposite the second substrate.

20. The method of claim 19, wherein forming the through silicon via further comprises forming the polymer layer over the conductive layer extending across the surface of the first substrate.