Method for fabricating embedded chips

• US 9,240,392 B2
• Filed: 04/09/2014
• Issued: 01/19/2016
• Est. Priority Date: 04/09/2014
• Status: Active Grant

• Current Assignee: Zhuhai Access Semiconductor Company Limited
• Original Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
• Inventors: Hurwitz, Dror, Huang, Alex
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): Lu, Farun
• Application Number:
  US14/249,282
• Publication Number:
  US 20150294896A1
• Time in Patent Office: 650 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/00 Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/042 the devices being arranged next to each other solar cells H01L31/042
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/071 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/3511 Warping
• CPC Class Codes: H01L 2933/005 relating to encapsulations

Abstract

A method of fabricating embedded die packages including the following steps: obtaining a honeycomb array of chip sockets such that each chip socket is surrounded by a framework having a polymer matrix of a first polymer and at least one via post through the framework around each socket; placing the honeycomb array on a transparent tape so that an underside of the honey comb array contacts the transparent tape; positioning a chip terminal the down (flip chip) in each chip socket so that undersides of the dies contact the transparent tape; using optical imaging through the tape to align the chips with the via posts; applying a packing material over and around the chips in the honeycomb array, and curing the filler to embed the chips on five sides; thinning and planarizing the packing material to expose upper ends of the vias on upper side of the array; removing the transparent tape; applying a feature layer of conductors on the underside of the honeycomb array and the undersides of the chips, to couple at least one terminal of each die to at least one through via; applying a feature layer of conductors on over side of the honeycomb array such that at least one conductor extends from a through via at least partway over each chip; dicing the array to create separate dies comprising at least one embedded chip having a contract pad coupled to a through via adjacent the chip.

Claims

1. A method of fabricating embedded die packages comprising:

obtaining an array of chip sockets such that each chip socket is surrounded by a framework having a polymer matrix of a first polymer and at least one via post through the framework around each socket;

Placing said array with framework on a transparent tape so that an underside of the array of chip sockets contacts said transparent tape;

positioning a chip terminal side down in each chip socket so that undersides of said chips contact said transparent tape;

Aligning said chips with said via posts by optical imaging through the tape;

Applying a packing material over and around said chips in said array, and curing the packing material to embed the chips on five sides;

Thinning and planarizing the packing material to expose upper ends of said vias on upper side of said array;

Removing the transparent tape;

Applying a feature layer of conductors on said underside of said array of chip sockets and said undersides of the chips, to couple at least one terminal of each die to at least one through via;

Applying a feature layer of conductors on over side of said array of chip sockets such that at least one conductor extends from a through via at least partway over each chip, and

dicing said array to create separate dies comprising at least one embedded chip having a contact pad coupled to a through via adjacent said chip.

2. The method of claim 1, wherein said array comprises an array of oblong cells.

3. The method of claim 1, wherein the chips comprise at least one of analog processors, digital processors, sensors, filters and memories.

4. The method of claim 1, wherein the framework comprises glass fiber reinforcements in said first polymer.

5. The method of claim 1, wherein the framework comprises a weave of glass fiber bundles in said first polymer.

6. The method of claim 1, wherein the packing material comprises a second polymer matrix.

7. The method of claim 1, wherein the packing material comprises a molding compound.

8. The method of claim 1, wherein the packing material comprises at least one polymer sheet that is laid over the framework and chips and is hot pressed.

9. The method of claim 6 wherein the packing material further comprises at least one of a particle filler and a chopped fiber filler.

10. The method of claim 1, wherein the array of chip sockets is fabricated by;

obtaining a sacrificial carrier;

laying down a layer of photoresist;

patterning the photoresist with a grid of copper vias;

plating copper via posts into the grid;

Stripping away the photoresist

laminating the copper via posts with a polymer dielectric;

thinning and planarizing the polymer dielectric to expose ends of the copper vias;

removing the carrier, and

machining chip sockets in the polymer dielectric.

11. The method of claim 10, wherein the sacrificial carrier is a copper carrier that is removed by dissolving the copper.

12. The method of claim 10 further comprising applying an etch-resistant layer over the carrier prior to depositing copper vias.

13. The method of claim 10, wherein the planarized polymer dielectric with exposed ends of copper vias is protected with an etch resistant material whilst the copper carrier is etched away.

14. The method of claim 13 wherein the etch resistant material is a photoresist.

15. The method of claim 11 wherein the polymer dielectric further comprises a weave of bundles of glass fibers and is applied as a pre-preg and is then cured.

16. The method of claim 1, wherein the array of chip sockets is fabricated by:

obtaining a sacrificial carrier;

laying down a layer of photoresist;

patterning the photoresist with a grid of copper vias and with an array of sockets;

plating copper via posts into the grid and the array;

Stripping away the photoresist;

laminating the copper via posts and the array with a polymer dielectric;

thinning and planarizing the polymer dielectric to expose ends of copper vias and array;

shielding the ends of the copper vias and selectively dissolving the array to form the sockets, and

removing the carrier.

17. The method of claim 1, wherein the honeycomb array is fabricated by:

obtaining a substrate comprising a copper clad polymer matrix;

drilling an array of via holes;

electroplating copper into the via holes;

removing copper cladding, and

machining sockets through the substrate.

18. The method of claim 17 wherein the step of removing the copper cladding comprises at least one of dissolving, abrasion and plasma etching.

19. The method of claim 17 wherein the polymer matrix further comprises glass fibers.

20. The method of claim 17 wherein the step of machining away sockets comprises at least one of punching and CNC.