Memory with off-chip controller

• US 9,240,405 B2
• Filed: 04/19/2011
• Issued: 01/19/2016
• Est. Priority Date: 04/19/2011
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Shih-Hung, Lue, Hang-Ting, Hsieh, Kuang Yeu
• Primary Examiner(s): Cao, Phat X
• Assistant Examiner(s): Vieira, Diana C
• Application Number:
  US13/089,652
• Publication Number:
  US 20120267689A1
• Time in Patent Office: 1,736 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

Claims

1. A method for manufacturing a memory device, the method comprising:

forming a memory circuit on a first substrate comprising an array of memory cells having a plurality of word lines and a plurality of bit lines, the memory circuit having a first interconnect surface with a first set of interconnect locations, the first set of interconnect locations including interconnect locations electrically connected by conductors to corresponding word lines in the plurality of word lines, and interconnect locations electrically connected by conductors to bit lines in the plurality of bit lines, wherein said conductors to corresponding word lines in the plurality of word lines include extensions parallel to the word lines and overlying bit lines in the plurality of bit lines;

forming a peripheral circuit on a second substrate including sense amplifiers and circuits configured to provide control signals for operation of the memory circuit to the plurality of word lines and the plurality of bit lines, the peripheral circuit having a second interconnect surface with a second set of interconnect locations electrically connected by conductors to the peripheral circuit; and

joining the first interconnect surface of the memory circuit to the second interconnect surface of the peripheral circuit.

2. The method of claim 1, wherein the second interconnect surface overlies the first interconnect surface upon the joining of the first interconnect surface to the second interconnect surface.

3. The method of claim 1, wherein:

forming the memory circuit includes performing a first manufacturing process to form the array of memory cells on the first substrate; and

forming the peripheral circuit includes performing a second manufacturing process to form the peripheral circuitry on the second substrate, the second manufacturing process different from the first manufacturing process.

4. The method of claim 1, wherein the joining comprises bonding the first interconnect surface directly to the second interconnect surface.

5. The method of claim 1, wherein interconnect locations in the first set of interconnect locations are arranged in a pattern on the first interconnect surface that corresponds to a pattern of interconnect locations in the second set of interconnect locations on the second interconnect surface, such that interconnect locations in the first set of interconnect locations are aligned with the corresponding interconnect locations in the second set of interconnect locations upon the joining of the first interconnect surface to the second interconnect surface.

6. The method of claim 1, further wherein joining the first interconnect surface to the second interconnect surface comprises:

joining the first interconnect surface of the memory circuit to an interposer, such that interconnect locations in the first set of interconnect locations are electrically connected to corresponding conductive members on the interposer; and

joining the second interconnect surface of the peripheral circuit to the interposer, such that interconnect locations in the second set of interconnect locations are electrically connected to corresponding conductive members on the interposer.

7. The method of claim 1, wherein:

forming the memory circuit and forming the peripheral circuit includes forming one of the memory circuit and the peripheral circuit on a substrate, and removing the one of the memory circuit and the peripheral circuit from the substrate; and

joining the first interconnect surface to the second interconnect surface comprises mating the one of the memory circuit and the peripheral circuit to the other of the memory circuit and the peripheral circuit upon removal from the substrate.

8. The method of claim 1, wherein the peripheral circuit is configured to generate first operational signals to operate a first memory cell in the plurality of memory cells, and to generate second operational signals to operate a second memory cell in the plurality of memory cells, the first operational signals different from the second operational signals.

9. The method of claim 1, wherein:

the memory circuit includes the first mentioned array of memory cells and a second array of memory cells, the first mentioned array and the second array having separate word lines and separate bit lines and having different access timing, the first set of interconnect locations including interconnect locations electrically connected by conductors to corresponding word lines in the separate word lines of the second array and interconnect locations electrically connected by conductors to the separate bit lines of the second array; and

the peripheral circuit is configured to apply different timing to the first array and the second array.

10. A memory device comprising:

a memory circuit on a first substrate comprising an array of memory cells having a plurality of word lines and a plurality of bit lines, the memory circuit having a first interconnect surface with a first set of interconnect locations, the first set of interconnect locations including interconnect locations electrically connected by conductors to corresponding word lines in the plurality of word lines and interconnect locations electrically connected by conductors to bit lines in the plurality of bit lines, wherein said conductors to corresponding word lines in the plurality of word lines include extensions parallel to the word lines and overlying bit lines in the plurality of bit lines; and

a peripheral circuit on a second substrate including sense amplifiers and a circuit configured to provide control signals for operation of the memory circuit to the plurality of word lines and the plurality of bit lines, the peripheral circuit having a second interconnect surface with a second set of interconnect locations electrically connected by conductors to the peripheral circuit;

wherein the second interconnect surface of the peripheral circuit is joined to the first interconnect surface of the memory circuit by an interconnect interface.

11. The device of claim 10, wherein the second interconnect surface overlies the first interconnect surface.

12. The device of claim 10, wherein the interconnect interface includes a direct bond of the second interconnect surface to the first interconnect surface.

13. The device of claim 10, wherein interconnect locations in the first set of interconnect locations are arranged in a pattern on the first interconnect surface that corresponds to a pattern of interconnect locations in the second set of interconnect locations on the second interconnect surface, such that interconnect locations in the first set of interconnect locations are aligned with the corresponding interconnect locations in the second set of interconnect locations.

14. The device of claim 10, the interconnect interface comprising an interposer having first and second sides and conductive members extending between the first and second sides, and wherein:

the first interconnect surface of the memory circuit is joined to the first side of the interposer, such that interconnect locations in the first set of interconnect locations are electrically connected to corresponding conductive members on the first side of the interposer; and

the second interconnect surface of the peripheral circuit is joined to the second side of the interposer, such that interconnect locations in the second set of interconnect locations are electrically connected to corresponding conductive members on the second side of the interposer.

15. The device of claim 10, wherein the peripheral circuit is configured to generate first operational signals to operate a first memory cell in the plurality of memory cells, and to generate second operational signals to operate a second memory cell in the plurality of memory cells, the first operational signals being different from the second operational signals.

16. The device of claim 10, wherein:

the memory circuit includes the first mentioned array of memory cells and a second array of memory cells, the first mentioned array and the second array having separate word lines and separate bit lines and having different access timing, the first set of interconnect locations including interconnect locations electrically connected by conductors to corresponding word lines in the separate word lines of the second array and interconnect locations electrically connected by conductors to the separate bit lines of the second array; and

the peripheral circuit is configured to apply different timing to the first mentioned array and the second array.