Transverse ultra-thin insulated gate bipolar transistor having high current density

• US 9,240,469 B2
• Filed: 12/27/2012
• Issued: 01/19/2016
• Est. Priority Date: 11/07/2012
• Status: Active Grant

• Current Assignee: Southeast University
• Original Assignee: Southeast University
• Inventors: Sun, Weifeng, Zhu, Jing, Xu, Shen, Qian, Qinsong, Liu, Siyang, Lu, Shengli, Shi, Longxing
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US14/439,715
• Publication Number:
  US 20150270377A1
• Time in Patent Office: 1,118 Days
• Field of Search: 257/141
• US Class Current: 1/1
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0808 of lateral transistors
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1008 of lateral transistors
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

Claims

1. A transverse ultra-thin insulated gate bipolar transistor having high current density, comprising:

a P substrate (1), wherein the P substrate (1) is provided with a buried oxide layer (2) thereon, the buried oxide layer (2) is provided with an N epitaxial layer (3) thereon, the thickness of the N epitaxial layer (3) is 0.1 to 1.5 μ

m, the N epitaxial layer (3) is provided with an N well region (4) and a P base region (6a) therein, the N well region (4) is provided with an N buffer region (5) therein, the N well region (4) is provided with a field oxide layer (11) thereon, a boundary of the N buffer region (5) abuts against a boundary of the field oxide layer (11), the N buffer region (5) is provided with a P drain region (9) therein, and the P base region (6a) is provided with a first P contact region (7a) and an N source region (8a) therein, wherein the N epitaxial layer (3) is provided therein with a P base region array (17) comprising a P annular base region (6b), the P base region array (17) is located between the N well region (4) and the P base region (6a), the P annular base region (6b) is provided with a second P contact region (7b) and an N annular source region (8b) therein, the second P contact region (7b) is located in the N annular source region (8b), a first polysilicon gate (12a) is disposed on a surface of a boundary region on which the field oxide layer (11) and the N annular source region (8b) are adjacent, the first polysilicon gate (12) extends from the boundary of the field oxide layer (11) towards a direction of the N annular source region (8b) to a place above the N annular source region (8b), a first gate oxide layer (10a) is disposed below an extension region of the first polysilicon gate (12a), a second polysilicon gate (12b) is disposed above the N epitaxial layer (3), a boundary of the second polysilicon gate (12b) extends to the place above the N annular source region (8b), another boundary of the second polysilicon gate (12b) extends to a place above the N source region (8a), a second gate oxide layer (10b) is disposed below the second polysilicon gate (12b), a dielectric isolation oxide layer (13) is disposed on the field oxide layer (11), the first polysilicon gate (12a), the second polysilicon gate (12b), the P base region (6a), the P annular base region (6b), the first P contact region (7a), the N source region (8a), the second P contact region (7b), the N annular source region (8b), the N buffer region (5), and the P drain region (9), an emitter metal wire (14) is connected to the first P contact region (7a), the N source region (8a), the second P contact region (7b), and the N annular source region (8b), a collector metal wire (15) is connected to the P drain region (9), and a gate metal wire (16) is connected to the first polysilicon gate (12a) and the second polysilicon gate (12b).

2. The transverse ultra-thin insulated gate bipolar transistor having high current density according to claim 1, wherein the P base region array (17) comprising the P annular base region (6b) is a P base region array having one column.

3. The transverse ultra-thin insulated gate bipolar transistor having high current density according to claim 1, wherein the P annular base region (6b) is hexagonal, quadrilateral, or circular.

4. The transverse ultra-thin insulated gate bipolar transistor having high current density according to claim 1, wherein a spacing between adjacent boundaries of the P base region (6a) and the P annular base region (6b) is 0.5 to 3 μ

m.

5. The transverse ultra-thin insulated gate bipolar transistor having high current density according to claim 1, wherein a spacing between adjacent boundaries of adjacent P annular base regions (6b) is 1 to 6 μ

m.

6. The transverse ultra-thin insulated gate bipolar transistor having high current density according to claim 2, wherein the P annular base region (6b) is hexagonal, quadrilateral, or circular.