Semiconductor device and method for fabricating semiconductor device
First Claim
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1. A semiconductor device, comprising:
- a first dielectric film formed above a semiconductor substrate;
a floating gate portion formed above the first dielectric film, a recess cutting into an inner portion of a side face of the floating gate portion being formed on the side face of the floating gate portion, the floating gate portion including first semiconductor films and a second semiconductor film arranged between the first semiconductor films, the second semiconductor film having different etching selectivity from that of the first semiconductor films, the recess being formed in a side face of the second semiconductor film and not being formed in side faces of the first semiconductor films;
a second dielectric film for element isolation of semiconductor elements arranged on a side of the side face of the floating gate portion and embedded between a height position of a lower portion of the side face of the floating gate portion and a height position inside the semiconductor substrate, the second dielectric film covering a greater part of a side face of a first semiconductor film of a lower side of the first semiconductor films;
a third dielectric film formed to cover an upper surface of the floating gate portion and a side face portion of the floating gate portion up to a height position of an upper surface of the second dielectric film, of the side face of the floating gate portion continuing from the upper surface of the floating gate portion, and also on the second dielectric film; and
a control gate portion formed above the third dielectric film,wherein a height position of an interface between the second dielectric film and the third dielectric film is provided between a height position in the recess and a position in a predetermined range below the height position in the recess.
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Abstract
A semiconductor device including a first dielectric film, a floating gate portion, second and third dielectric films, a control gate portion, and a recess on the side face of the floating gate portion. The second dielectric film for element isolation is embedded between a height position of a lower portion of the side face of the floating gate portion and a height position inside the semiconductor substrate. The third dielectric film covers an upper surface and a side face portion of the floating gate portion up to a height position of an upper surface of the second dielectric film, and on the second dielectric film. A height position of an interface between the second and third dielectric films is between a height position of a center of the recess and a position in a predetermined range below the height position of the center of the recess.
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Citations
9 Claims
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1. A semiconductor device, comprising:
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a first dielectric film formed above a semiconductor substrate; a floating gate portion formed above the first dielectric film, a recess cutting into an inner portion of a side face of the floating gate portion being formed on the side face of the floating gate portion, the floating gate portion including first semiconductor films and a second semiconductor film arranged between the first semiconductor films, the second semiconductor film having different etching selectivity from that of the first semiconductor films, the recess being formed in a side face of the second semiconductor film and not being formed in side faces of the first semiconductor films; a second dielectric film for element isolation of semiconductor elements arranged on a side of the side face of the floating gate portion and embedded between a height position of a lower portion of the side face of the floating gate portion and a height position inside the semiconductor substrate, the second dielectric film covering a greater part of a side face of a first semiconductor film of a lower side of the first semiconductor films; a third dielectric film formed to cover an upper surface of the floating gate portion and a side face portion of the floating gate portion up to a height position of an upper surface of the second dielectric film, of the side face of the floating gate portion continuing from the upper surface of the floating gate portion, and also on the second dielectric film; and a control gate portion formed above the third dielectric film, wherein a height position of an interface between the second dielectric film and the third dielectric film is provided between a height position in the recess and a position in a predetermined range below the height position in the recess. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsArisumi, Osamu, Iinuma, Toshihiko
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Primary Examiner(s)WHALEN, DANIEL B
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Application NumberUS13/713,766Publication NumberTime in Patent Office1,132 DaysField of SearchUS Class Current1/1CPC Class CodesH01L 29/40114 the electrodes comprising a...H01L 29/42336 with one gate at least part...H01L 29/66825 with a floating gate H01L29...H01L 29/788 with floating gate H01L29/7...H01L 29/7881 Programmable transistors wi...H10B 41/30 characterised by the memory...
