Motor drive control using pulse-width modulation pulse skipping

• US 9,240,749 B2
• Filed: 08/09/2013
• Issued: 01/19/2016
• Est. Priority Date: 08/10/2012
• Status: Active Grant

• Current Assignee: Copeland Corporation LLC (Emerson Electric Company)
• Original Assignee: Emerson Climate Technologies Incorporated (Emerson Electric Company)
• Inventors: Green, Charles E., Marcinkiewicz, Joseph G.
• Primary Examiner(s): GLASS, ERICK DAVID
• Application Number:
  US13/963,317
• Publication Number:
  US 20140042948A1
• Time in Patent Office: 893 Days
• Field of Search: 318/503
• US Class Current: 1/1
• CPC Class Codes: H02P 2201/15 Power factor correction [PFC] circuit generating the DC link voltage for motor driving inverter
• CPC Class Codes: H02P 2205/05 Torque loop, i.e. comparison of the motor torque with a torque reference
• CPC Class Codes: H02P 2205/07 Speed loop, i.e. comparison of the motor speed with a speed reference
• CPC Class Codes: H02P 23/14 Estimation or adaptation of motor parameters, e.g. rotor time constant, flux, speed, current or voltage
• CPC Class Codes: H02P 23/26 Power factor control [PFC]
• CPC Class Codes: H02P 23/30 Direct torque control [DTC] or field acceleration method [FAM]
• CPC Class Codes: H02P 27/04 using variable-frequency supply voltage, e.g. inverter or converter supply voltage
• CPC Class Codes: H02P 27/08 with pulse width modulation
• CPC Class Codes: H02P 27/085 wherein the PWM mode is adapted on the running conditions of the motor, e.g. the switching frequency

Abstract

A control system for a motor includes a pulse-width modulation module, a pulse skip determination module, and a duty cycle adjustment module. The pulse-width modulation module generates three duty cycle values based on three voltage requests, respectively. A plurality of solid-state switches control three phases of the motor in response to the three duty cycle values, respectively. The pulse skip determination module generates a pulse skip signal. The duty cycle adjustment module selectively prevents the plurality of solid-state switches from switching during intervals specified by the pulse skip signal.

Claims

1. A control system for a motor, the control system comprising:

a pulse-width modulation module that generates three duty cycle values based respectively on three voltage requests and based on a bus voltage;

a mode determination module that selectively enables a pulse skipping mode based on a speed of the motor;

a pulse skip determination module that, in response to the pulse skipping mode being enabled, serially generates pulse skipping numbers, wherein the pulse skipping numbers are selected randomly from a group consisting of zero, one, and two;

a duty cycle adjustment module that, for each switching period of a plurality of switching periods, selectively sets the three duty cycle values to a zero value in response to a corresponding one of the pulse skipping numbers being nonzero;

a pulse module that, for each of the switching periods, generates three pulse waveforms in response to the three duty cycle values as modified by the duty cycle adjustment module; and

an inverter power module that controls three phases of the motor based on the three pulse waveforms, respectively.

2. A control system for a motor, the control system comprising:

a pulse-width modulation module that generates three duty cycle values based on three voltage requests, respectively, wherein a plurality of solid-state switches control three phases of the motor in response to the three duty cycle values, respectively;

a pulse skip determination module that generates a pulse skip signal; and

a duty cycle adjustment module that selectively prevents the plurality of solid-state switches from switching during intervals specified by the pulse skip signal.

3. The control system of claim 2 wherein the pulse-width modulation module generates each of the three duty cycle values based on a ratio of each of the three voltage requests, respectively, to a voltage of a bus, wherein the bus provides power to the motor via the plurality of solid-state switches.

4. The control system of claim 2 further comprising a mode determination module that generates a mode signal in response to at least one motor operating parameter, wherein in response to the mode signal being in a first state, the duty cycle adjustment module prevents the plurality of solid-state switches from switching during intervals specified by the pulse skip signal.

5. The control system of claim 4 wherein the motor operating parameter is a speed of the motor, and wherein the mode determination module sets the mode signal to the first state in response to the speed of the motor being less than a predetermined threshold.

6. The control system of claim 2 further comprising a pulse module that generates three pulse waveforms using duty cycles set by the three duty cycle values, respectively, wherein the plurality of solid-state switches are controlled based on the three pulse waveforms.

7. The control system of claim 6 wherein the duty cycle adjustment module selectively prevents the plurality of solid-state switches from switching by causing the pulse module to generate the three pulse waveforms using duty cycles of 0%.

8. The control system of claim 2 wherein the pulse skip determination module generates the pulse skip signal based on a series of integer values, wherein the duty cycle adjustment module prevents the plurality of solid-state switches from switching in response to the pulse skip signal having a first state.

9. The control system of claim 8 wherein the pulse skip determination module generates the pulse skip signal having the first state in response to a present one of the series of integer values being nonzero.

10. The control system of claim 8 wherein the series of integer values is a predetermined sequence.

11. The control system of claim 8 further comprising a random number generator that generates the series of integer values.

12. A method of controlling a motor, the method comprising:

generating three duty cycle values based on three voltage requests, respectively, wherein a plurality of solid-state switches control three phases of the motor in response to the three duty cycle values, respectively;

generating a pulse skip signal; and

selectively preventing the plurality of solid-state switches from switching during intervals specified by the pulse skip signal.

13. The method of claim 12 further comprising generating each of the three duty cycle values based on a ratio of each of the three voltage requests, respectively, to a voltage of a bus, wherein the bus provides power to the motor via the plurality of solid-state switches.

14. The method of claim 12 further comprising:

generating a mode signal in response to at least one motor operating parameter; and

in response to the mode signal being in a first state, preventing the plurality of solid-state switches from switching during intervals specified by the pulse skip signal.

15. The method of claim 14 wherein the motor operating parameter is a speed of the motor, and further comprising setting the mode signal to the first state in response to the speed of the motor being less than a predetermined threshold.

16. The method of claim 12 further comprising generating three pulse waveforms using duty cycles set by the three duty cycle values, respectively, wherein the plurality of solid-state switches are controlled based on the three pulse waveforms.

17. The method of claim 16 wherein the selectively preventing the plurality of solid-state switches from switching is performed by causing the three pulse waveforms to be generated using duty cycles of 0%.

18. The method of claim 12 further comprising:

generating the pulse skip signal based on a series of integer values; and

preventing the plurality of solid-state switches from switching in response to the pulse skip signal having a first state.

19. The method of claim 18 further comprising generating the pulse skip signal having the first state in response to a present one of the series of integer values being nonzero.

20. The method of claim 18 wherein the series of integer values is a predetermined sequence.

21. The method of claim 18 further comprising randomly generating the series of integer values.