Three dimensional integrated circuits

• US 9,240,790 B2
• Filed: 08/13/2014
• Issued: 01/19/2016
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): CAMPBELL, SHAUN M
• Application Number:
  US14/458,939
• Publication Number:
  US 20140346571A1
• Time in Patent Office: 524 Days
• Field of Search: 257/686
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Claims

1. An integrated circuit comprising:

a substrate;

a first plurality of layers including a first programmable circuit;

a second plurality of layers including a pattern of metal layers based on a predetermined logical functionality for the integrated circuit; and

a third plurality of layers including a second programmable circuit;

wherein the first plurality of layers, the second plurality of layers, and the third plurality of layers are formed in a stacked manner, which utilizes a plurality of integrated circuit fabrication masks, on the substrate; and

wherein the pattern of metal layers is configured to hard-wire the first programmable circuit and the second programmable circuit with the predetermined logical functionality by converting programmable logic to hard-wired logic.

2. The integrated circuit of claim 1, wherein the pattern of metal layers is configured to connect to a logic low source and to a logic high source and is configured to propagate a logic low signal and a logic high signal to the first programmable circuit and the second programmable circuit.

3. The integrated circuit of claim 1, wherein the pattern of metal layers is based on predetermined timing characteristics.

4. The integrated circuit of claim 1, wherein a variation of the pattern is based on a different predetermined logical functionality for the integrated circuit.

5. The integrated circuit of claim 1, wherein the predetermined logical functionality corresponds to a logical functionality of a reprogrammable device in a programmed state.

6. The integrated circuit of claim 5, wherein the reprogrammable device comprises one of a field programmable gate array (FPGA) device or a programmable logic device (PLD).

7. The integrated circuit of claim 5, wherein the pattern facilitates operation as an application specific integrated circuit (ASIC) hard-wired with the predetermined logical functionality.

8. A method comprising:

forming an integrated circuit including a substrate, wherein said forming the integrated circuit comprises;

forming in a stacked manner that utilizes a plurality of integrated circuit fabrication masks on the substrate a first plurality of layers including a first programmable circuit;

forming in the stacked manner that utilizes the plurality of integrated circuit fabrication masks on the substrate a second plurality of layers including a pattern of metal layers based on a predetermined logical functionality for the integrated circuit; and

forming in the stacked manner that utilizes the plurality of integrated circuit fabrication masks on the substrate a third plurality of layers including a second programmable circuit, wherein the pattern of metal layers is configured to hard-wire the first programmable circuit and the second programmable circuit with the predetermined logical functionality by converting programmable logic to hard-wired logic.

9. The method of claim 8, wherein the pattern of metal layers is configured to connect to a logic low source and to a logic high source and is configured to propagate a logic low signal and a logic high signal to the first programmable circuit and the second programmable circuit.

10. The method of claim 8, wherein the pattern of metal layers is based on predetermined timing characteristics.

11. The method of claim 8, wherein a variation of the pattern is based on a different predetermined logical functionality for the integrated circuit.

12. The method of claim 8, wherein the predetermined logical functionality corresponds to a logical functionality of a reprogrammable device in a programmed state.

13. The method of claim 12, wherein the reprogrammable device comprises one of a field programmable gate array (FPGA) device or a programmable logic device (PLD).

14. The method of claim 12, wherein the pattern facilitates operation as an application specific integrated circuit (ASIC) hard-wired with the predetermined logical functionality.

15. An integrated circuit comprising:

a substrate;

a first plurality of layers including a plurality of programmable logic circuits;

a second plurality of layers including a pattern of metal layers based on a predetermined logical functionality for the integrated circuit; and

a third plurality of layers including a plurality of programmable routing circuits;

wherein the first plurality of layers, the second plurality of layers, and the third plurality of layers are formed in a stacked manner, which utilizes a plurality of integrated circuit fabrication masks, on the substrate; and

wherein the pattern of metal layers is configured to hard-wire the plurality of programmable logic circuits and the plurality of programmable routing circuits with the predetermined logical functionality by converting programmable logic to hard-wired logic.

16. The integrated circuit of claim 15, wherein the pattern of metal layers is configured to connect to a logic low source and to a logic high source and is configured to propagate a logic low signal and a logic high signal to the plurality of programmable logic circuits and the plurality of programmable routing circuits, and wherein the pattern of metal layers is based on predetermined timing characteristics.

17. The integrated circuit of claim 15, wherein a variation of the pattern is based on a different predetermined logical functionality for the integrated circuit.

18. The integrated circuit of claim 15, wherein the predetermined logical functionality corresponds to a logical functionality of a reprogrammable device in a programmed state.

19. The integrated circuit of claim 18, wherein the reprogrammable device comprises one of a field programmable gate array (FPGA) device or a programmable logic device (PLD).

20. The integrated circuit of claim 18, wherein the pattern facilitates operation as an application specific integrated circuit (ASIC) hard-wired with the predetermined logical functionality.