Three dimensional integrated circuits
First Claim
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1. An integrated circuit comprising:
- a substrate;
a first plurality of layers including a first programmable circuit;
a second plurality of layers including a pattern of metal layers based on a predetermined logical functionality for the integrated circuit; and
a third plurality of layers including a second programmable circuit;
wherein the first plurality of layers, the second plurality of layers, and the third plurality of layers are formed in a stacked manner, which utilizes a plurality of integrated circuit fabrication masks, on the substrate; and
wherein the pattern of metal layers is configured to hard-wire the first programmable circuit and the second programmable circuit with the predetermined logical functionality by converting programmable logic to hard-wired logic.
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Abstract
A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
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Citations
20 Claims
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1. An integrated circuit comprising:
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a substrate; a first plurality of layers including a first programmable circuit; a second plurality of layers including a pattern of metal layers based on a predetermined logical functionality for the integrated circuit; and a third plurality of layers including a second programmable circuit; wherein the first plurality of layers, the second plurality of layers, and the third plurality of layers are formed in a stacked manner, which utilizes a plurality of integrated circuit fabrication masks, on the substrate; and wherein the pattern of metal layers is configured to hard-wire the first programmable circuit and the second programmable circuit with the predetermined logical functionality by converting programmable logic to hard-wired logic. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
forming an integrated circuit including a substrate, wherein said forming the integrated circuit comprises; forming in a stacked manner that utilizes a plurality of integrated circuit fabrication masks on the substrate a first plurality of layers including a first programmable circuit; forming in the stacked manner that utilizes the plurality of integrated circuit fabrication masks on the substrate a second plurality of layers including a pattern of metal layers based on a predetermined logical functionality for the integrated circuit; and forming in the stacked manner that utilizes the plurality of integrated circuit fabrication masks on the substrate a third plurality of layers including a second programmable circuit, wherein the pattern of metal layers is configured to hard-wire the first programmable circuit and the second programmable circuit with the predetermined logical functionality by converting programmable logic to hard-wired logic. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An integrated circuit comprising:
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a substrate; a first plurality of layers including a plurality of programmable logic circuits; a second plurality of layers including a pattern of metal layers based on a predetermined logical functionality for the integrated circuit; and a third plurality of layers including a plurality of programmable routing circuits; wherein the first plurality of layers, the second plurality of layers, and the third plurality of layers are formed in a stacked manner, which utilizes a plurality of integrated circuit fabrication masks, on the substrate; and wherein the pattern of metal layers is configured to hard-wire the plurality of programmable logic circuits and the plurality of programmable routing circuits with the predetermined logical functionality by converting programmable logic to hard-wired logic. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification