Systems and processes for decoding chain reaction codes through inactivation

• US 9,240,810 B2
• Filed: 08/28/2009
• Issued: 01/19/2016
• Est. Priority Date: 06/11/2002
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Digital Fountain Incorporated (Qualcomm, Inc.)
• Inventors: Shokrollahi, Amin, Lassen, Soren, Karp, Richard
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US12/549,560
• Publication Number:
  US 20110103519A1
• Time in Patent Office: 2,335 Days
• Field of Search: 341 50- 52, 341/94, 714/746, 714/751, 714/752, 714/786
• US Class Current: 1/1
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/3761 using code combining, i.e. using combining of codeword portions which may have been transmitted separately, e.g. Digital Fountain codes, Raptor codes or Luby Transform [LT] codes

Abstract

A method for processing a chain reaction code includes first selecting a source symbol which is associated with an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one.

Claims

1. A decoder configured to function in a chain reaction code communication system wherein an encoder generates a plurality of multi-stage output symbols that are check symbols and generates a plurality of source symbols, wherein each of the check symbols is associated with one or more source symbols, the check symbols associated with one or more source symbols referred to as check symbols of degree one or higher, wherein at least one check symbol is associated with at least two source symbols, the check symbols associated with two or more source symbols referred to as check symbols of degree two or higher, and wherein at least one source symbol is marked as active, the decoder comprising:

(i) a selector configured to select one of the active source symbols associated with a check symbol of degree two or higher; and

(ii) an activate module communicatively coupled to the selector and configured to deactivate the selected source symbol associated with a check symbol of degree two or higher.

2. The decoder of claim 1, wherein a transmitter transmits the one or more source symbols to a receiver, the decoder further comprising:

a processor communicatively coupled to the activate module and configured to infer the check symbols without having to receive them from the transmitter; and

to use the inferred check symbols to check that the one or more source symbols were received correctly.

3. A decoder for decoding input symbols from output symbols, wherein output symbols are generated at an encoder for source symbols derived from the input symbols and check symbols associated with source symbols, wherein a degree of a check symbol is the number of source symbols associated with that check symbol and the degree of check symbols can be one or more than one, the decoder comprising:

a receiver configured to receive output symbols and check symbols; and

a processor communicatively coupled to the receiver and configured to mark source symbols as active to indicate that it is to be decoded from received output symbols and check symbols;

mark at least one of the active source symbols that is associated with a check symbol of degree two or higher as an inactive source symbol;

decode, in part, the received source symbols, by decoding the active source symbols;

determine a process for decoding the inactive source symbols; and

to decode the inactive source symbols.

4. The decoder of claim 3, wherein the check symbols are generated according to a parity code.

5. The decoder of claim 3, wherein the check symbols are generated according to an LDPC code.

6. A decoder for decoding source symbols from output symbols, wherein output symbols are generated at an encoder derived from the source symbols, wherein a degree of an output symbol is the number of source symbols associated with that output symbol, the decoder comprising:

a receiver configured to (i) receive a first set of output symbols; and

a processor communicatively coupled to the receiver and configured to;

(ii) recover source symbols from the output symbols contained in the first set of output symbols;

(iii) deactivate one or more unrecovered source symbols associated with an output symbol of degree two or higher thereby reducing the degree of any output symbol associated with a deactivated source symbol by one;

(iv) repeat (ii) and (iii) until all of the output symbols in the first set of output symbols have been used; and

(v) decode the source symbols that have been deactivated.

7. The decoder of claim 6, wherein

the processor is further configured to:

(vi) determine if all of the source symbols have been recovered; and

(vii) request a second set of output symbols if it is determined that not all of the source symbols have been recovered;

the receiver is further configured to (viii) receive a second set of output symbols; and

the processor and the receiver are further configured to (ix) repeat (ii)-(viii) on the second set of output symbols until all of the source symbols have been recovered.

8. The decoder of claim 6, wherein

the receiver is further configured to (vi) receive a second set of output symbols;

and

the processor is further configured to (vii) merge the second set of output symbols into the first set of output symbols.

9. The decoder of claim 8, wherein (vi) and (vii) are configured to occur substantially concurrently with (ii)-(v).

10. The decoder of claim 9, wherein (ii)-(vii) repeat until all of the source symbols have been recovered.

11. A decoder that receives multi-stage output symbols, wherein the multi-stage output symbols are generated at an encoder derived from output symbols and check symbols, wherein the output symbols are generated at an encoder derived from source symbols, wherein a degree of an output symbol is the number of source symbols associated with that output symbol, wherein a degree of a check symbol is the number of source symbols associated with that check symbol, the decoder comprising:

a receiver configured to (i) receive a first set of multi-stage output symbols wherein at least one of the multi-stage output symbols in the first set of multi-stage output symbols comprises a check symbol and at least one of the multi-stage output symbols in the first set of output symbols comprises an output symbol; and

a processor communicatively coupled to the receiver and configured to;

(ii) recover source symbols from the output symbols contained in the first set of multistage output symbols;

(iii) deactivate one or more unrecovered source symbols associated with an output symbol of degree two or higher thereby reducing the degree of any output symbol associated with a deactivated source symbol by one;

(iv) repeat (ii) and (iii) until all of the output symbols in the first set of output symbols have been used;

(v) decode the source symbols that have been deactivated; and

(vi) recover check symbols from the check symbols in the first set of multi-stage output symbols.

12. The decoder of claim 11, wherein

the processor is further configured to:

(vii) determine if all of the source symbols have been recovered; and

(viii) request a second set of multi-stage output symbols if it is determined that not all of the source symbols have been recovered;

the receiver is further configured to (ix) receive a second set of multi-stage output symbols; and

the processor and the receiver are further configured to (x) repeat (ii)-(ix) on the second set of multi-stage output symbols until all of the source symbols have been recovered.

13. The decoder of claim 12, wherein the processor and the receiver are further configured to (xi) repeat (ii)-(ix) on the second set of multi-stage output symbols until all of the check symbols have been recovered.

14. The decoder of claim 11, wherein

the receiver is further configured to (vii) receive a second set of multi-stage output symbols;

and

the processor is further configured to (viii) merge the second set of multi-stage output symbols into the first set of multi-stage output symbols.

15. The decoder of claim 14, wherein (vii) and (viii) occur substantially concurrently with steps (ii)-(vi).

16. The decoder of claim 15, wherein (ii)-(viii) repeat until all of the source symbols have been recovered.

17. The decoder of claim 16, wherein (ii)-(viii) repeat until all of the check symbols have been recovered.

18. The decoder of claim 15, wherein (vi) can be interrupted in favor of (ii) if new output symbols containing source symbols are received.

19. A non-transitory computer program product in a chain reaction code communication system wherein an encoder generates a plurality of multi-stage output symbols that are check symbols and generates a plurality of source symbols, wherein each of the check symbols is associated with one or more source symbols, the check symbols associated with one or more source symbols referred to as check symbols of degree one or higher, wherein at least one check symbol is associated with at least two source symbols, the check symbols associated with two or more source symbols referred to as check symbols of degree two or higher, and wherein at least one source symbol is marked as active, the computer program product comprising:

a processor-readable medium storing processor-readable instructions configured to cause a processor to;

(i) select one of the active source symbols associated with a check symbol of degree two or higher; and

(ii) deactivate the selected source symbol associated with a check symbol of degree two or higher.

20. The product of claim 19, wherein a transmitter transmits the one or more source symbols to a receiver, and the instructions are further configured to cause the processor to:

infer, at a decoder at the receiver, the check symbols without having to receive them from the transmitter; and

use the inferred check symbols to check that the one or more source symbols were received correctly.

21. A non-transitory computer program product for decoding input symbols from output symbols, wherein output symbols are generated at an encoder for source symbols derived from the input symbols and check symbols associated with source symbols, wherein a degree of a check symbol is the number of source symbols associated with that check symbol and the degree of check symbols can be one or more than one, the computer program product comprising:

a processor-readable medium storing processor-readable instructions configured to cause a processor to;

receive output symbols and check symbols;

mark source symbols as active to indicate that it is to be decoded from received output symbols and check symbols;

mark at least one of the active source symbols that is associated with a check symbol of degree two or higher as an inactive source symbol;

decode, in part, the received source symbols, by decoding the active source symbols;

determine a process for decoding the inactive source symbols; and

decode the inactive source symbols.

22. The product of claim 21, wherein the check symbols are generated according to a parity code.

23. The product of claim 21, wherein the check symbols are generated according to an LDPC code.

24. A non-transitory computer program product for decoding source symbols from output symbols, wherein output symbols are generated at an encoder derived from the source symbols, wherein a degree of an output symbol is the number of source symbols associated with that output symbol, the computer program product comprising:

a processor-readable medium storing processor-readable instructions configured to cause a processor to;

(i) receive a first set of output symbols;

(ii) recover source symbols from the output symbols contained in the first set of output symbols;

(iii) deactivate one or more unrecovered source symbols associated with an output symbol of degree two or higher thereby reducing the degree of any output symbol associated with a deactivated source symbol by one;

(iv) repeat steps (ii) and (iii) until all of the output symbols in the first set of output symbols have been used; and

(v) decode the source symbols that have been deactivated.

25. The product of claim 24, wherein the instructions are further configured to cause the processor to:

(vi) determine if all of the source symbols have been recovered;

(vii) request a second set of output symbols if it is determined that not all of the source symbols have been recovered;

(viii) receive a second set of output symbols; and

(ix) repeat steps (ii)-(viii) on the second set of output symbols until all of the source symbols have been recovered.

26. The product of claim 24, wherein the instructions are further configured to cause the processor to:

(vi) receive a second set of output symbols; and

(vii) merge the second set of output symbols into the first set of output symbols.

27. The product of claim 26, wherein steps (vi) and (vii) occur substantially concurrently with steps (ii)-(v).

28. The product of claim 27, wherein steps (ii)-(vii) repeat until all of the source symbols have been recovered.

29. A non-transitory computer program product for processing multi-stage output symbols, wherein the multi-stage output symbols are generated at an encoder derived from output symbols and check symbols, wherein the output symbols are generated at an encoder derived from source symbols, wherein a degree of an output symbol is the number of source symbols associated with that output symbol, wherein a degree of a check symbol is the number of source symbols associated with that check symbol, the computer program product comprising:

a processor-readable medium storing processor-readable instructions configured to cause a processor to;

(i) receive a first set of multi-stage output symbols wherein at least one of the multi-stage output symbols in the first set of multi-stage output symbols comprises a check symbol and at least one of the multi-stage output symbols in the first set of output symbols comprises an output symbol;

(ii) recover source symbols from the output symbols contained in the first set of multistage output symbols;

(iii) deactivate one or more unrecovered source symbols associated with an output symbol of degree two or higher thereby reducing the degree of any output symbol associated with a deactivated source symbol by one;

(iv) repeat steps (ii) and (iii) until all of the output symbols in the first set of output symbols have been used;

(v) decode the source symbols that have been deactivated; and

(vi) recover check symbols from the check symbols in the first set of multi-stage output symbols.

30. The product of claim 29, wherein the instructions are further configured to cause the processor to:

(vii) determine if all of the source symbols have been recovered;

(viii) request a second set of multi-stage output symbols if it is determined that not all of the source symbols have been recovered;

(ix) receive a second set of multi-stage output symbols; and

(x) repeat steps (ii)-(ix) on the second set of multi-stage output symbols until all of the source symbols have been recovered.

31. The product of claim 30, wherein the instructions are further configured to cause the processor to (xi) repeat steps (ii)-(ix) on the second set of multi-stage output symbols until all of the check symbols have been recovered.

32. The product of claim 29, wherein the instructions are further configured to cause the processor to:

(vii) receive a second set of multi-stage output symbols; and

(viii) merge the second set of multi-stage output symbols into the first set of multi-stage output symbols.

33. The product of claim 32, wherein steps (vii) and (viii) occur substantially concurrently with steps (ii)-(vi).

34. The product of claim 33, wherein steps (ii)-(viii) repeat until all of the source symbols have been recovered.

35. The product of claim 34, wherein steps (ii)-(viii) repeat until all of the check symbols have been recovered.

36. The product of claim 33, wherein step (vi) can be interrupted in favor of step (ii) if new output symbols containing source symbols are received.