Apparatus and methods facilitating power regulation for an implantable device
First Claim
1. An implantable device, comprising:
- a substrate that forms at least part of a body of the implantable device; and
a circuit disposed on or within the substrate and comprising;
a high load power regulator configured to provide a first current level to one or more components of the implantable device;
a low load power regulator configured to provide a second current level to the one or more components of the implantable device, wherein the second current level is lower that the first current level; and
a regulator switch configured to simultaneously enable or disable current draw from the high load power regulator and the low load power regulator as a function of power state and associated power requirement of the one or more or more components of the implantable device, such that the first current level can be provided to at least a first of the one or more components while simultaneously providing the second current level to at least a second of the one or more components.
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Accused Products
Abstract
Apparatus and methods configured to perform power regulation for an implantable device are presented. In an aspect, an implantable device can include a substrate that forms at least part of a body of the implantable device and a circuit disposed on or within the substrate. The circuit can include a high load power regulator configured to provide a first current level to components of the implantable device and a low load power regulator configured to provide a second current level to components of the implantable device, wherein the second current level is lower that the first current level. The circuit can also include a regulator switch configured to enable or disable current draw from the high load power regulator and the low load power regulator as a function of power state and associated power requirement of the components of the implantable device.
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Citations
28 Claims
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1. An implantable device, comprising:
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a substrate that forms at least part of a body of the implantable device; and a circuit disposed on or within the substrate and comprising; a high load power regulator configured to provide a first current level to one or more components of the implantable device; a low load power regulator configured to provide a second current level to the one or more components of the implantable device, wherein the second current level is lower that the first current level; and a regulator switch configured to simultaneously enable or disable current draw from the high load power regulator and the low load power regulator as a function of power state and associated power requirement of the one or more or more components of the implantable device, such that the first current level can be provided to at least a first of the one or more components while simultaneously providing the second current level to at least a second of the one or more components. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A power regulation system for an implantable medical device, comprising:
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a processor operatively coupled to the implantable medical device; a non-transitory computer readable medium that stores computer executable components, wherein the non-transitory computer readable medium comprises flash memory; a central processing unit (CPU) power regulator configured to provide a first current level to the processor; an analog power regulator configured to provide a second current level to the processor, wherein the second current level is lower that the first current level; a flash power regulator configured to provide a third current level to the flash memory; and a regulator switch configured to enable or disable current draw from the CPU power regulator and the analog power regulator as a function of a power state of the processor, wherein the third current level is higher than the first current level, and wherein the regulator switch is configured to enable current draw from the flash power regulator and disable current draw from the analog power regulator and CPU power regulator in response to programming or erasing of the flash memory. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method comprising:
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providing, via an analog power regulator, a first current level to at least one analog component of the processer of an implantable device in response to digital components of the processor being in an off state; receiving a trigger signal indicating a request to turn on digital operation of the digital components, and in response to the receiving the trigger signal; turning on operation of a central processing unit (CPU) power regulator; turning on the digital operation of the digital components; providing, via the CPU power regulator, a second current level to the processor, wherein the second current level is higher than the first current level; simultaneously enabling current draw from the analog power regulator and the CPU power regulator such that the first current level can be provided to the at least one analog component and the second current level can be provided to digital components as a function of power state and associated power requirement of the components of the processor; and powering the digital operation of the digital components via the CPU power regulator. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A power regulation system for an implantable medical device, comprising:
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a processor operatively coupled to the implantable medical device; a non-transitory computer readable medium that stores computer executable components; a central processing unit (CPU) power regulator configured to provide a first current level to the processor, wherein the CPU power regulator is configured to turn on before the processor is turned on in response to receipt of a signal indicating an event that requires the processor to be turned on; an analog power regulator configured to provide a second current level to the processor, wherein the second current level is lower that the first current level; a regulator switch configured to enable or disable current draw from the CPU power regulator and the analog power regulator as a function of a power state of the processor; a delay component configured to effect a delay to digital operation of the processor to allow the CPU power regulator to stabilize, wherein the regulator switch is configured to enable current draw from the CPU power regulator after the CPU power regulator stabilizes; and a high frequency oscillator configured to provide a first dynamic current to the CPU regulator in response to turning on of the CPU power regulator, wherein the high frequency oscillator and the CPU power regulator are configured to turn off and the regulator switch are configured to enable current draw from the analog power regulator in response to receipt of a signal indicating completion of the event.
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Specification